From ea7d91e9d340655acbf4ef5f62b8762b262dc83d Mon Sep 17 00:00:00 2001
From: RuigeLee <wut.ruigeli@gmail.com>
Date: Thu, 11 Sep 2025 15:15:47 +0800
Subject: [PATCH] =?UTF-8?q?=E6=A3=80=E5=9B=9E=E7=BC=96=E8=AF=91=E6=96=87?=
 =?UTF-8?q?=E4=BB=B6?=
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---
 src/test/scala/test.scala | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)
 create mode 100644 src/test/scala/test.scala

diff --git a/src/test/scala/test.scala b/src/test/scala/test.scala
new file mode 100644
index 0000000..f20ef2a
--- /dev/null
+++ b/src/test/scala/test.scala
@@ -0,0 +1,23 @@
+package test
+
+
+import BACK._
+
+
+import chisel3._
+import chisel3.stage._
+
+
+
+
+
+object testShinModule extends App {
+  (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/shin/", "-e", "verilog" ) ++ args, Seq(
+      ChiselGeneratorAnnotation(() => { new ShinTop }),
+    ))
+
+  (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/SimCDR/", "-e", "verilog" ) ++ args, Seq(
+      ChiselGeneratorAnnotation(() => { new SimCDR }),
+    ))
+}
+