输出IO扩展为16个

src/main/verilog/backBoardSlvTop.v

@@ -16,7 +16,7 @@ module slave_top(
   output lvds_down_dout_n,
 
   // inout [31:0] digitalIO
-  output [7:0] digitalIO
+  output [15:0] digitalIO
 
 );
 
@@ -142,7 +142,8 @@ CLKDIV Inst5_CLKDIVC(
 //   end
 // endgenerate
 
-assign digitalIO = out[7:0];
+assign digitalIO = out[15:0];
+assign in = 32'hAA55AA55;
 
 BackBoardSlvDigitalIO i_BackBoardSlvDigitalIO(
   .reset(~rst_n),