From ea226e913a06c65c8433352edb90e30e2ad5268d Mon Sep 17 00:00:00 2001 From: RuigeLee Date: Wed, 6 Mar 2024 17:10:51 +0800 Subject: [PATCH] =?UTF-8?q?=E8=BE=93=E5=87=BAIO=E6=89=A9=E5=B1=95=E4=B8=BA?= =?UTF-8?q?16=E4=B8=AA?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- src/main/verilog/backBoardSlvTop.v | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/main/verilog/backBoardSlvTop.v b/src/main/verilog/backBoardSlvTop.v index 6061d6b..7add6b9 100644 --- a/src/main/verilog/backBoardSlvTop.v +++ b/src/main/verilog/backBoardSlvTop.v @@ -16,7 +16,7 @@ module slave_top( output lvds_down_dout_n, // inout [31:0] digitalIO - output [7:0] digitalIO + output [15:0] digitalIO ); @@ -142,7 +142,8 @@ CLKDIV Inst5_CLKDIVC( // end // endgenerate -assign digitalIO = out[7:0]; +assign digitalIO = out[15:0]; +assign in = 32'hAA55AA55; BackBoardSlvDigitalIO i_BackBoardSlvDigitalIO( .reset(~rst_n),