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输出IO扩展为16个

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RuigeLee
2024-03-06 17:10:51 +08:00
parent dba35faa6e
commit ea226e913a
1 changed files with 3 additions and 2 deletions
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5
src/main/verilog/backBoardSlvTop.v
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@@ -16,7 +16,7 @@ module slave_top(
output lvds_down_dout_n, output lvds_down_dout_n,
// inout [31:0] digitalIO // inout [31:0] digitalIO
output [7:0] digitalIO output [15:0] digitalIO
); );
@@ -142,7 +142,8 @@ CLKDIV Inst5_CLKDIVC(
// end // end
// endgenerate // endgenerate
assign digitalIO = out[7:0]; assign digitalIO = out[15:0];
assign in = 32'hAA55AA55;
BackBoardSlvDigitalIO i_BackBoardSlvDigitalIO( BackBoardSlvDigitalIO i_BackBoardSlvDigitalIO(
.reset(~rst_n), .reset(~rst_n),