tx 首尾修正

src/main/scala/Switch/mac/MAC.scala

@@ -756,7 +756,7 @@ val rxethmac = withClockAndReset(io.mii.mrx_clk_pad_i.asClock, io.asyncReset)( M
   TxEndFrm        := macTileLinkTx.io.TxEndFrm
   TxData          := macTileLinkTx.io.TxData
 
-  macTileLinkTx.io.TxEndFrm_wb := wishbone.io.TxEndFrm_wb
+  // macTileLinkTx.io.TxEndFrm_wb := wishbone.io.TxEndFrm_wb
   
               wishbone.io.TxUsedData      := TxUsedData
   macTileLinkTx.io.TxUsedData := TxUsedData

src/main/scala/Switch/mac/MacTileLinkTx.scala

@@ -7,6 +7,7 @@ import chisel3.util._
 class TxFifo_Stream_Bundle extends Bundle{
   val data = UInt(8.W)
   val isStart = Bool()
+  val isLast  = Bool()
 }
 
 
@@ -29,7 +30,7 @@ class MacTileLinkTxIO extends Bundle{
   val TxDone         = Input(Bool())      // Transmission ended
 
 
-  val TxEndFrm_wb = Input(Bool())
+  // val TxEndFrm_wb = Input(Bool())
 }
 
 
@@ -46,8 +47,6 @@ class MacTileLinkTx extends Module with RequireAsyncReset{
   val TxData     = RegInit(0.U(8.W)); io.TxData     := TxData
   val LastWord = RegInit(false.B)
   val ReadTxDataFromFifo_tck = RegInit(false.B); 
-  // io.ReadTxDataFromFifo_tck := ReadTxDataFromFifo_tck
-  
 
   // Generating delayed signals
   val TxAbort_q    = RegNext( io.TxAbort, false.B)
@@ -71,8 +70,8 @@ class MacTileLinkTx extends Module with RequireAsyncReset{
   // Indication of the last word
   when( (TxEndFrm | io.TxAbort | io.TxRetry) & Flop ){
     LastWord := false.B
-  } .elsewhen( io.TxUsedData & Flop ){
-    LastWord := io.TxEndFrm_wb
+  } .elsewhen( io.txReq.fire ){
+    LastWord := io.txReq.bits.isLast
   }
 
   // Tx end frame generation
@@ -89,8 +88,10 @@ class MacTileLinkTx extends Module with RequireAsyncReset{
       io.TxUsedData & Flop & ~LastWord |
       TxStartFrm & io.TxUsedData & Flop
 
-
+  when( io.txReq.fire ){
     TxData := io.txReq.bits.data    
+  }
+
 
   assert( ~(io.txReq.ready & ~io.txReq.valid) )
 

src/main/scala/Switch/mac/MacTilelink.scala

@@ -33,7 +33,7 @@ abstract class MacTileLinkBase() extends Module{
 
     val txReq = Decoupled(new TxFifo_Stream_Bundle)
 
-    val TxEndFrm_wb = Output(Bool())
+    // val TxEndFrm_wb = Output(Bool())
 
 
     // Tx Status signals
@@ -131,7 +131,7 @@ abstract class MacTileLinkBase() extends Module{
 
 
   val TxStartFrm_wb = RegInit(false.B)
-  val TxEndFrm_wb = RegInit(false.B); io.TxEndFrm_wb := TxEndFrm_wb
+  val TxEndFrm_wb = RegInit(false.B)//; io.TxEndFrm_wb := TxEndFrm_wb
 
   val TxLength = RegInit(0.U(16.W))
   val LatchedTxLength = RegInit(0.U(16.W))
@@ -203,7 +203,7 @@ abstract class MacTileLinkBase() extends Module{
 
 
 
-
+  io.txReq.bits.isLast  := TxEndFrm_wb
   io.txReq.bits.data    := io.txDeq.data.bits
   io.txReq.bits.isStart := TxStartFrm_wb
   io.txReq.valid        := io.txDeq.data.valid