100 lines
2.6 KiB
Scala
100 lines
2.6 KiB
Scala
package MAC
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import chisel3._
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import chisel3.util._
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class TxFifo_Stream_Bundle extends Bundle{
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val data = UInt(8.W)
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val isStart = Bool()
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val isLast = Bool()
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}
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class MacTileLinkTxIO extends Bundle{
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val txReq = Flipped(Decoupled(new TxFifo_Stream_Bundle))
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// val txResp = Decoupled()
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val RstDeferLatched = Output(Bool())
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val BlockingTxStatusWrite_sync = Input(Bool())
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val TxStartFrm = Output(Bool()) // Transmit packet start frame
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val TxEndFrm = Output(Bool()) // Transmit packet end frame
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val TxData = Output(UInt(8.W)) // Transmit packet data byte
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val TxUsedData = Input(Bool()) // Transmit packet used data
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val TxRetry = Input(Bool()) // Transmit packet retry
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val TxAbort = Input(Bool()) // Transmit packet abort
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val TxDone = Input(Bool()) // Transmission ended
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// val TxEndFrm_wb = Input(Bool())
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}
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class MacTileLinkTx extends Module with RequireAsyncReset{
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val io = IO(new MacTileLinkTxIO)
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io.RstDeferLatched := io.BlockingTxStatusWrite_sync & ~RegNext(io.BlockingTxStatusWrite_sync, false.B)
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val TxStartFrm = RegInit(false.B); io.TxStartFrm := TxStartFrm
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val TxEndFrm = RegInit(false.B); io.TxEndFrm := TxEndFrm
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val TxData = RegInit(0.U(8.W)); io.TxData := TxData
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val LastWord = RegInit(false.B)
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val ReadTxDataFromFifo_tck = RegInit(false.B);
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// Generating delayed signals
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val TxAbort_q = RegNext( io.TxAbort, false.B)
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val TxRetry_q = RegNext( io.TxRetry, false.B)
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val TxUsedData_q = RegNext( io.TxUsedData, false.B)
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// Changes for tx occur every second clock. Flop is used for this manner.
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val Flop = RegInit(false.B)
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when( io.TxDone | io.TxAbort | TxRetry_q){
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Flop := false.B
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} .elsewhen ( io.TxUsedData ){
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Flop := ~Flop
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}
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when( io.txReq.valid & io.txReq.bits.isStart ){
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TxStartFrm := true.B
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} .elsewhen(TxUsedData_q | io.TxRetry & (~TxRetry_q) | io.TxAbort & (~TxAbort_q) ){
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TxStartFrm := false.B
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}
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// Indication of the last word
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when( (TxEndFrm | io.TxAbort | io.TxRetry) & Flop ){
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LastWord := false.B
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} .elsewhen( io.txReq.fire ){
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LastWord := io.txReq.bits.isLast
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}
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// Tx end frame generation
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when(Flop & TxEndFrm | io.TxAbort | TxRetry_q){
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TxEndFrm := false.B
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} .elsewhen(Flop & LastWord){
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TxEndFrm := true.B
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}
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io.txReq.ready :=
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io.txReq.valid & io.txReq.bits.isStart & ~TxStartFrm |
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io.TxUsedData & Flop & ~LastWord |
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TxStartFrm & io.TxUsedData & Flop
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when( io.txReq.fire ){
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TxData := io.txReq.bits.data
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}
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assert( ~(io.txReq.ready & ~io.txReq.valid) )
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}
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