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tx 首尾修正

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This commit is contained in:
RuigeLee
2023-10-24 16:27:30 +08:00
parent 701ba16491
commit e99ff4789f
3 changed files with 16 additions and 15 deletions
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2
src/main/scala/Switch/mac/MAC.scala
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@@ -756,7 +756,7 @@ val rxethmac = withClockAndReset(io.mii.mrx_clk_pad_i.asClock, io.asyncReset)( M
TxEndFrm := macTileLinkTx.io.TxEndFrm TxEndFrm := macTileLinkTx.io.TxEndFrm
TxData := macTileLinkTx.io.TxData TxData := macTileLinkTx.io.TxData
macTileLinkTx.io.TxEndFrm_wb := wishbone.io.TxEndFrm_wb // macTileLinkTx.io.TxEndFrm_wb := wishbone.io.TxEndFrm_wb
wishbone.io.TxUsedData := TxUsedData wishbone.io.TxUsedData := TxUsedData
macTileLinkTx.io.TxUsedData := TxUsedData macTileLinkTx.io.TxUsedData := TxUsedData

13
src/main/scala/Switch/mac/MacTileLinkTx.scala
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@@ -7,6 +7,7 @@ import chisel3.util._
class TxFifo_Stream_Bundle extends Bundle{ class TxFifo_Stream_Bundle extends Bundle{
val data = UInt(8.W) val data = UInt(8.W)
val isStart = Bool() val isStart = Bool()
val isLast = Bool()
} }
@@ -29,7 +30,7 @@ class MacTileLinkTxIO extends Bundle{
val TxDone = Input(Bool()) // Transmission ended val TxDone = Input(Bool()) // Transmission ended
val TxEndFrm_wb = Input(Bool()) // val TxEndFrm_wb = Input(Bool())
} }
@@ -46,8 +47,6 @@ class MacTileLinkTx extends Module with RequireAsyncReset{
val TxData = RegInit(0.U(8.W)); io.TxData := TxData val TxData = RegInit(0.U(8.W)); io.TxData := TxData
val LastWord = RegInit(false.B) val LastWord = RegInit(false.B)
val ReadTxDataFromFifo_tck = RegInit(false.B); val ReadTxDataFromFifo_tck = RegInit(false.B);
// io.ReadTxDataFromFifo_tck := ReadTxDataFromFifo_tck
// Generating delayed signals // Generating delayed signals
val TxAbort_q = RegNext( io.TxAbort, false.B) val TxAbort_q = RegNext( io.TxAbort, false.B)
@@ -71,8 +70,8 @@ class MacTileLinkTx extends Module with RequireAsyncReset{
// Indication of the last word // Indication of the last word
when( (TxEndFrm | io.TxAbort | io.TxRetry) & Flop ){ when( (TxEndFrm | io.TxAbort | io.TxRetry) & Flop ){
LastWord := false.B LastWord := false.B
} .elsewhen( io.TxUsedData & Flop ){ } .elsewhen( io.txReq.fire ){
LastWord := io.TxEndFrm_wb LastWord := io.txReq.bits.isLast
} }
// Tx end frame generation // Tx end frame generation
@@ -89,8 +88,10 @@ class MacTileLinkTx extends Module with RequireAsyncReset{
io.TxUsedData & Flop & ~LastWord | io.TxUsedData & Flop & ~LastWord |
TxStartFrm & io.TxUsedData & Flop TxStartFrm & io.TxUsedData & Flop
when( io.txReq.fire ){
TxData := io.txReq.bits.data
}
TxData := io.txReq.bits.data
assert( ~(io.txReq.ready & ~io.txReq.valid) ) assert( ~(io.txReq.ready & ~io.txReq.valid) )

16
src/main/scala/Switch/mac/MacTilelink.scala
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@@ -33,7 +33,7 @@ abstract class MacTileLinkBase() extends Module{
val txReq = Decoupled(new TxFifo_Stream_Bundle) val txReq = Decoupled(new TxFifo_Stream_Bundle)
val TxEndFrm_wb = Output(Bool()) // val TxEndFrm_wb = Output(Bool())
// Tx Status signals // Tx Status signals
@@ -131,7 +131,7 @@ abstract class MacTileLinkBase() extends Module{
val TxStartFrm_wb = RegInit(false.B) val TxStartFrm_wb = RegInit(false.B)
val TxEndFrm_wb = RegInit(false.B); io.TxEndFrm_wb := TxEndFrm_wb val TxEndFrm_wb = RegInit(false.B)//; io.TxEndFrm_wb := TxEndFrm_wb
val TxLength = RegInit(0.U(16.W)) val TxLength = RegInit(0.U(16.W))
val LatchedTxLength = RegInit(0.U(16.W)) val LatchedTxLength = RegInit(0.U(16.W))
@@ -151,11 +151,11 @@ abstract class MacTileLinkBase() extends Module{
} }
when(((TxLength - 1.U) === 0.U) & io.TxUsedData){ when(((TxLength - 1.U) === 0.U) & io.TxUsedData){
TxEndFrm_wb := true.B TxEndFrm_wb := true.B
} .elsewhen(txRetryPulse | txDonePulse | txAbortPulse){ } .elsewhen(txRetryPulse | txDonePulse | txAbortPulse){
TxEndFrm_wb := false.B TxEndFrm_wb := false.B
} }
when( io.txDeq.req.fire ){ when( io.txDeq.req.fire ){
@@ -203,7 +203,7 @@ abstract class MacTileLinkBase() extends Module{
io.txReq.bits.isLast := TxEndFrm_wb
io.txReq.bits.data := io.txDeq.data.bits io.txReq.bits.data := io.txDeq.data.bits
io.txReq.bits.isStart := TxStartFrm_wb io.txReq.bits.isStart := TxStartFrm_wb
io.txReq.valid := io.txDeq.data.valid io.txReq.valid := io.txDeq.data.valid