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Ruige Lee
2025-04-07 17:39:44 +08:00
parent 703ad172b8
commit e34338753a
3 changed files with 521 additions and 96 deletions
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320
src/main/scala/backBoard/shin/SlaveParser.scala
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@@ -3,127 +3,255 @@ package BACK
import chisel3._
import chisel3.util._
class FrameHeader extends Bundle{
val frameLenAim = UInt(12.W) //帧长度目标
val frameStyle = UInt(2.W) //包类型
}
class SubMsgHeader extends Bundle{
val subMsg_devIndex = UInt(14.W) // 子报文中设备索引
val subMsg_style = UInt(2.W) // 子报文类型
val subMsg_address = UInt(16.W) //子报文地址
val subMsg_operator = UInt(4.W) //子报文命令类型
val subMsg_length = UInt(12.W) //子报文负载长度
val subMsg_workCnt = UInt(16.W) //子报文工作计数
}
class ShareSRAMIO extends Bundle{
val addr = Input(UInt(15.W))
val dataw = Input( UInt(8.W) )
val datar = Output( UInt(8.W) )
val enw = Input(Bool())
val enr = Input(Bool())
}
class SlaveParserIO extends Module{
val downOut = Decoupled(new AXIS_Bundle(8))
val downIn = Flipped( Decoupled(new AXIS_Bundle(8)) )
val downOut = Decoupled(new AXIS_Bundle(8))
val upOut = Decoupled(new AXIS_Bundle(8))
val upIn = Flipped( Decoupled(new AXIS_Bundle(8)) )
val upOut = Decoupled(new AXIS_Bundle(8))
val sram
val sram_r = for( 0 until 2 ) yield { Flipped(new ShareSRAMIO) }
val sram_w = for( 0 until 2 ) yield { Flipped(new ShareSRAMIO) }
}
abstract class SlaveParserBase extends Module{
val io: SlaveParserIO = IO(new SlaveParserIO)
val FRAME_STYLE_COMMON = 0.U
val FRAME_STYLE_PROBE = 1.U
val STATE_IDLE = 0.U //空闲
val STATE_HEADER = 1.U //长度/ /保留2bits //包类型
val STATE_PAYLOAD_INDEX_STYLE = 4.U //子报文设备索引 //子报文类型
val STATE_PAYLOAD_ADDR = 6.U //子报文地址
val STATE_PAYLOAD_OP_LENGTH = 7.U //子报文命令类型 //子报文长度
val STATE_PAYLOAD_WORKCNT = 9.U //子报文工作计数
val STATE_PAYLOAD_DATA = 10.U //子报文数据
val STATE_CRC = 11.U //CRC校验
val STATE_ERROR = 12.U //
val downStateNext = Wire(UInt(4.W))
val downStateCurr = RegNext(downStateNext, STATE_IDLE(4.W))
val lengthCnt = Reg(UInt(11.W)) //动态计数器
//val subMsgCnt = Reg(UInt(7.W)) //子报文不超过128个
val subMsgLenAim = Reg(UInt(12.W)) //子报文长度
val frameLenAim = Reg(UInt(12.W)) //帧长度目标
val frameLenCnt = Reg(UInt(12.W)) //帧长度计数
val isCrcPass: Bool
val isTxEnd: Bool
val isShortRx: Bool //接收长度小于预期
val frameStyle = Reg(UInt(2.W)) //包类型
val devIndex = Reg(UInt(14.W)) //当前设备索引
val subMsg_devIndex = Reg(UInt(14.W)) // 子报文中设备索引
val subMsg_style = Reg(UInt(2.W)) // 子报文类型
val subMsg_address = Reg(UInt(16.W)) //子报文地址
val subMsg_operator = Reg(UInt(4.W)) //子报文命令类型
val subMsg_length = Reg(UInt(12.W)) //子报文负载长度
val subMsg_workCnt = Reg(UInt(16.W)) //子报文工作计数
when( downStateCurr === STATE_HEADER & lengthCnt === 0.U ){
frameLenAim := io.downIn.bits.tdata << 4
} .elsewhen( downStateCurr === STATE_HEADER & lengthCnt === 1.U ){
frameLenAim := frameLenAim | io.downIn.bits.tdata(7,4)
frameStyle := io.downIn.bits.tdata(1,0)
}
val downRecParser = Module(new SlaveRecParser)
val upRecParser = Module(new SlaveRecParser)
when( downStateCurr === STATE_PAYLOAD_INDEX_STYLE & lengthCnt === 0.U ){
subMsg_devIndex := io.downIn.bits.tdata << 6
} .elsewhen( downStateCurr === STATE_PAYLOAD_INDEX_STYLE & lengthCnt === 1.U ){
subMsg_devIndex := subMsg_devIndex | io.downIn.bits.tdata(7,2)
subMsg_style := io.downIn.bits.tdata(1,0)
}
val downSendGen = Module(new SlaveSendGen)
val upSendGen = Module(new SlaveSendGen)
when( downStateCurr === STATE_PAYLOAD_ADDR & lengthCnt === 0.U ){
subMsg_address := io.downIn.bits.tdata << 8
} .elsewhen( downStateCurr === STATE_PAYLOAD_ADDR & lengthCnt === 1.U ){
subMsg_address := subMsg_address | io.downIn.bits.tdata
}
when( downStateCurr === STATE_PAYLOAD_OP_LENGTH & lengthCnt === 0.U ){
subMsg_operator := io.downIn.bits.tdata(7,4)
subMsg_length := io.downIn.bits.tdata(3,0) << 8
} .elsewhen( downStateCurr === STATE_PAYLOAD_OP_LENGTH & lengthCnt === 1.U ){
subMsg_length := subMsg_length | io.downIn.bits.tdata(7,0)
}
val downRecFifo = for( i <- 0 until 2 ) yield { Module(new Queue(UInt(8.W), 8)) }
val upRecFifo = for( i <- 0 until 2 ) yield { Module(new Queue(UInt(8.W), 8)) }
when( downStateCurr === STATE_PAYLOAD_WORKCNT & lengthCnt === 0.U ){
subMsg_workCnt := io.downIn.bits.tdata(7,0) << 8
} .elsewhen( downStateCurr === STATE_PAYLOAD_WORKCNT & lengthCnt === 1.U ){
subMsg_workCnt := subMsg_workCnt | io.downIn.bits.tdata(7,0)
val downSinkSel = Reg(Bool())
val upSinkSel = Reg(Bool())
val downFrameInfo = Reg(new FrameHeader)
val downSubMsgInfo = for( 0 until 2 ) yield { Reg(new SubMsgHeader) }
val upFrameInfo = Reg(new FrameHeader)
val upSubMsgInfo = for( 0 until 2 ) yield { Reg(new SubMsgHeader) }
val isDownSendBusy = downRecParser.io.frameReq.ready
val isUpSendBusy = upRecParser.io.frameReq.ready
val isDownSendPend = RegInit(false.B)
val isUpSendPend = RegInit(false.B)
//同时到来怎么办
when( downRecParser.io.frameReq.fire ){
when(downRecParser.io.frameReq.bits.frameStyle === FRAME_STYLE_PROBE){ //下行来了一个嗅探包
isUpSendPend := true.B
downFrameInfo := downRecParser.io.frameReq.bits
println("Warning! No busy protection!")
} .elsewhen( downRecParser.io.frameReq.bits.frameStyle === FRAME_STYLE_COMMON ){ //下行来了一个普通包
isDownSendPend := true.B
downFrameInfo := downRecParser.io.frameReq.bits
println("Warning! No busy protection!")
}
} .elsewhen( upRecParser.io.frameReq.fire ){
when( upRecParser.io.frameReq.bits.frameStyle === FRAME_STYLE_PROBE){ //上行来了一个嗅探包
println("Probe Resp!")
} .elsewhen( upRecParser.io.frameReq.bits.frameStyle === FRAME_STYLE_COMMON ){ //上行来了一个普通包
isUpSendPend := true.B
upFrameInfo := upRecParser.io.frameReq.bits
println("Warning! No busy protection!")
}
}
downStateNext :=
val isDownSendProbe: Bool //下行探针
val isUpSendProbe: Bool //上行探针
val probeFrame: FrameHeader //固定化探针内容
downSendGen.io.frameReq.valid :=
isDownSendPend | isDownSendProbe //下行转发 | 下行探针
assert( OneHot(isDownSendPend, isDownSendProbe) )
downSendGen.io.frameReq.bits := Mux1H(Seq(
isDownSendPend -> downFrameInfo, //下行转发
isDownSendProbe -> probeFrame, //下行探针
))
when( downSendGen.io.frameReq.fire ){
isDownSendPend := false.B
}
upSendGen.io.frameReq.valid :=
isUpSendPend | isUpSendProbe //上行转发 | 上行探针
assert( OneHot(isUpSendPend, isUpSendProbe) )
upSendGen.io.frameReq.bits := Mux1H(Seq(
isUpSendPend -> upFrameInfo, //上行转发
isUpSendProbe -> probeFrame, //上行探针
))
when( upSendGen.io.frameReq.fire ){
isUpSendPend := false.B
}
when( downSendGen.io.frameReq.fire ){
isDownSendPend := false.B
}
upSendFifo.io.enq.bits := Mux1H(Seq(
( downRecParser.io.frameStyle === FRAME_STYLE_PROBE & downRecParser.io.stateCurr > STATE_HEADER ) -> downRecParser.io.data.bits //嗅探包 bypass到上行
))
upSendFifo.io.enq.valid :=
((downRecParser.io.frameStyle === FRAME_STYLE_PROBE & downRecParser.io.stateCurr > STATE_HEADER ) & downRecParser.io.data.valid) |
downRecParser.io.data.ready :=
((downRecParser.io.frameStyle === FRAME_STYLE_PROBE & downRecParser.io.stateCurr > STATE_HEADER ) & upSendFifo.io.enq.ready ) |
downSendFifo.io.enq.bits := Mux1H(Seq(
( downRecParser.io.frameStyle === FRAME_STYLE_COMMON & downRecParser.io.stateCurr > STATE_HEADER ) ->
))
val isDownIdle
val isDownBypassToDown
val isDownWriteToSRAM
val isDownReadFromSRAM
val isDownLoopBack
val isUpIdle
val isUpBypassToUp
val isUpWriteToSRAM
val isUpReadFromSRAM
val isUpBlackHole
// val downOutFifo = Module(new Queue(UInt(8.W), 8))
val upInFifo = Module(new Queue(UInt(8.W), 8))
// val upOutFifo = Module(new Queue(UInt(8.W), 8))
downInFifo.io.enq <> io.downIn
io.downOut.valid :=
( === FRAME_STYLE_COMMON ) &
io.upOut.valid :=
( === FRAME_STYLE_PROBE) & |
io.upOut.bits :=
Mux1H(Seq(
//必须使用上升沿触发，以避免前一帧长度超过预期
( downStateCurr === STATE_IDLE ) -> Mux( ~RegNext(io.downIn.axis.valid) & io.downIn.axis.valid, STATE_HEADER, STATE_IDLE ),
( downStateCurr === STATE_HEADER ) -> Mux( isShortRx, STATE_ERROR,
Mux( lengthCnt === 0, STATE_HEADER,
MuxCase( STATE_ERROR, Array(
( io.downIn.axis.bits(1,0) === FRAME_STYLE_COMMON ) -> STATE_PAYLOAD_INDEX_STYLE,
( io.downIn.axis.bits(1,0) === FRAME_STYLE_PROBE ) -> STATE_CRC,
))
)
),
( downStateCurr === STATE_PAYLOAD_INDEX_STYLE ) -> Mux( isShortRx, STATE_ERROR,
Mux( lengthCnt === 0, STATE_PAYLOAD_INDEX_STYLE, STATE_PAYLOAD_ADDR )
),
( downStateCurr === STATE_PAYLOAD_ADDR ) -> Mux( isShortRx, STATE_ERROR,
Mux( lengthCnt === 0, STATE_PAYLOAD_ADDR, STATE_PAYLOAD_OP_LENGTH )
),
( downStateCurr === STATE_PAYLOAD_OP_LENGTH ) -> Mux( isShortRx, STATE_ERROR,
Mux( lengthCnt === 0, STATE_PAYLOAD_OP_LENGTH, STATE_PAYLOAD_WORKCNT )
),
( downStateCurr === STATE_PAYLOAD_WORKCNT ) -> Mux( isShortRx, STATE_ERROR,
Mux( lengthCnt === 0.U, STATE_PAYLOAD_WORKCNT, STATE_PAYLOAD_DATA )
),
( downStateCurr === STATE_PAYLOAD_DATA ) -> Mux( isShortRx, STATE_ERROR,
Mux( lengthCnt === (subMsgLen - 1.U),
Mux(frameLenCnt === frameLenAim, STATE_CRC, STATE_PAYLOAD_INDEX_STYLE
), STATE_PAYLOAD_DATA )
),
( downStateCurr === STATE_CRC ) -> Mux( isShortRx, STATE_ERROR,
Mux( lengthCnt === (4 - 1).U, Mux( isCrcPass, STATE_IDLE, STATE_ERROR), STATE_CRC )
),
( downStateCurr === STATE_ERROR ) -> Mux( isTxEnd, STATE_IDLE, STATE_ERROR ),
( === FRAME_STYLE_PROBE) -> downInFifo.io.deq.bits, //嗅探包情形
-> upInFifo.io.deq.bits, //上行
-> //上行修正数据
))
io.downOut.bits :=
Mux1H(Seq(
-> //自主发送嗅探包
( ) -> downInFifo.io.deq.bits, //下行
( ) -> //下行修正数据
))
downInFifo.io.deq.ready :=
upInFifo.io.deq.ready :=
// assert( ~(downStateCurr === STATE_HEADER & ~io.downIn.axis.fire), "Assert Failed!" )
// assert( ~(downStateCurr === STATE_PAYLOAD_INDEX_STYLE & ~io.downIn.axis.fire), "Assert Failed!" )
// assert( ~(downStateCurr === STATE_PAYLOAD_ADDR & ~io.downIn.axis.fire), "Assert Failed!" )
}