From e34338753aaf8a0b2c07d1dd73a759f36823e75c Mon Sep 17 00:00:00 2001 From: Ruige Lee Date: Mon, 7 Apr 2025 17:39:44 +0800 Subject: [PATCH] =?UTF-8?q?=E4=BB=8E=E7=AB=99=E6=94=B6=E5=8F=91=E6=A1=86?= =?UTF-8?q?=E6=9E=B6=E5=B7=B2=E6=88=90?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .../scala/backBoard/shin/SlaveParser.scala | 320 ++++++++++++------ .../scala/backBoard/shin/SlaveRecParser.scala | 151 +++++++++ .../scala/backBoard/shin/SlaveSendGen.scala | 146 ++++++++ 3 files changed, 521 insertions(+), 96 deletions(-) create mode 100644 src/main/scala/backBoard/shin/SlaveRecParser.scala create mode 100644 src/main/scala/backBoard/shin/SlaveSendGen.scala diff --git a/src/main/scala/backBoard/shin/SlaveParser.scala b/src/main/scala/backBoard/shin/SlaveParser.scala index f201a9b..1a1d78c 100644 --- a/src/main/scala/backBoard/shin/SlaveParser.scala +++ b/src/main/scala/backBoard/shin/SlaveParser.scala @@ -3,127 +3,255 @@ package BACK import chisel3._ import chisel3.util._ + +class FrameHeader extends Bundle{ + val frameLenAim = UInt(12.W) //帧长度目标 + val frameStyle = UInt(2.W) //包类型 +} + +class SubMsgHeader extends Bundle{ + val subMsg_devIndex = UInt(14.W) // 子报文中设备索引 + val subMsg_style = UInt(2.W) // 子报文类型 + val subMsg_address = UInt(16.W) //子报文地址 + val subMsg_operator = UInt(4.W) //子报文命令类型 + val subMsg_length = UInt(12.W) //子报文负载长度 + val subMsg_workCnt = UInt(16.W) //子报文工作计数 +} + + + +class ShareSRAMIO extends Bundle{ + val addr = Input(UInt(15.W)) + val dataw = Input( UInt(8.W) ) + val datar = Output( UInt(8.W) ) + val enw = Input(Bool()) + val enr = Input(Bool()) +} + + + class SlaveParserIO extends Module{ - val downOut = Decoupled(new AXIS_Bundle(8)) val downIn = Flipped( Decoupled(new AXIS_Bundle(8)) ) + val downOut = Decoupled(new AXIS_Bundle(8)) - val upOut = Decoupled(new AXIS_Bundle(8)) val upIn = Flipped( Decoupled(new AXIS_Bundle(8)) ) + val upOut = Decoupled(new AXIS_Bundle(8)) - val sram + val sram_r = for( 0 until 2 ) yield { Flipped(new ShareSRAMIO) } + val sram_w = for( 0 until 2 ) yield { Flipped(new ShareSRAMIO) } } abstract class SlaveParserBase extends Module{ val io: SlaveParserIO = IO(new SlaveParserIO) - val FRAME_STYLE_COMMON = 0.U - val FRAME_STYLE_PROBE = 1.U - val STATE_IDLE = 0.U //空闲 - val STATE_HEADER = 1.U //长度/ /保留2bits //包类型 - val STATE_PAYLOAD_INDEX_STYLE = 4.U //子报文设备索引 //子报文类型 - val STATE_PAYLOAD_ADDR = 6.U //子报文地址 - val STATE_PAYLOAD_OP_LENGTH = 7.U //子报文命令类型 //子报文长度 - val STATE_PAYLOAD_WORKCNT = 9.U //子报文工作计数 - val STATE_PAYLOAD_DATA = 10.U //子报文数据 - val STATE_CRC = 11.U //CRC校验 - val STATE_ERROR = 12.U // - - - val downStateNext = Wire(UInt(4.W)) - val downStateCurr = RegNext(downStateNext, STATE_IDLE(4.W)) - - val lengthCnt = Reg(UInt(11.W)) //动态计数器 - //val subMsgCnt = Reg(UInt(7.W)) //子报文不超过128个 - val subMsgLenAim = Reg(UInt(12.W)) //子报文长度 - val frameLenAim = Reg(UInt(12.W)) //帧长度目标 - val frameLenCnt = Reg(UInt(12.W)) //帧长度计数 - val isCrcPass: Bool - val isTxEnd: Bool - val isShortRx: Bool //接收长度小于预期 - val frameStyle = Reg(UInt(2.W)) //包类型 val devIndex = Reg(UInt(14.W)) //当前设备索引 - val subMsg_devIndex = Reg(UInt(14.W)) // 子报文中设备索引 - val subMsg_style = Reg(UInt(2.W)) // 子报文类型 - val subMsg_address = Reg(UInt(16.W)) //子报文地址 - val subMsg_operator = Reg(UInt(4.W)) //子报文命令类型 - val subMsg_length = Reg(UInt(12.W)) //子报文负载长度 - val subMsg_workCnt = Reg(UInt(16.W)) //子报文工作计数 - when( downStateCurr === STATE_HEADER & lengthCnt === 0.U ){ - frameLenAim := io.downIn.bits.tdata << 4 - } .elsewhen( downStateCurr === STATE_HEADER & lengthCnt === 1.U ){ - frameLenAim := frameLenAim | io.downIn.bits.tdata(7,4) - frameStyle := io.downIn.bits.tdata(1,0) - } + val downRecParser = Module(new SlaveRecParser) + val upRecParser = Module(new SlaveRecParser) - when( downStateCurr === STATE_PAYLOAD_INDEX_STYLE & lengthCnt === 0.U ){ - subMsg_devIndex := io.downIn.bits.tdata << 6 - } .elsewhen( downStateCurr === STATE_PAYLOAD_INDEX_STYLE & lengthCnt === 1.U ){ - subMsg_devIndex := subMsg_devIndex | io.downIn.bits.tdata(7,2) - subMsg_style := io.downIn.bits.tdata(1,0) - } + val downSendGen = Module(new SlaveSendGen) + val upSendGen = Module(new SlaveSendGen) - when( downStateCurr === STATE_PAYLOAD_ADDR & lengthCnt === 0.U ){ - subMsg_address := io.downIn.bits.tdata << 8 - } .elsewhen( downStateCurr === STATE_PAYLOAD_ADDR & lengthCnt === 1.U ){ - subMsg_address := subMsg_address | io.downIn.bits.tdata - } - when( downStateCurr === STATE_PAYLOAD_OP_LENGTH & lengthCnt === 0.U ){ - subMsg_operator := io.downIn.bits.tdata(7,4) - subMsg_length := io.downIn.bits.tdata(3,0) << 8 - } .elsewhen( downStateCurr === STATE_PAYLOAD_OP_LENGTH & lengthCnt === 1.U ){ - subMsg_length := subMsg_length | io.downIn.bits.tdata(7,0) - } + val downRecFifo = for( i <- 0 until 2 ) yield { Module(new Queue(UInt(8.W), 8)) } + val upRecFifo = for( i <- 0 until 2 ) yield { Module(new Queue(UInt(8.W), 8)) } - when( downStateCurr === STATE_PAYLOAD_WORKCNT & lengthCnt === 0.U ){ - subMsg_workCnt := io.downIn.bits.tdata(7,0) << 8 - } .elsewhen( downStateCurr === STATE_PAYLOAD_WORKCNT & lengthCnt === 1.U ){ - subMsg_workCnt := subMsg_workCnt | io.downIn.bits.tdata(7,0) + + val downSinkSel = Reg(Bool()) + val upSinkSel = Reg(Bool()) + + val downFrameInfo = Reg(new FrameHeader) + val downSubMsgInfo = for( 0 until 2 ) yield { Reg(new SubMsgHeader) } + + val upFrameInfo = Reg(new FrameHeader) + val upSubMsgInfo = for( 0 until 2 ) yield { Reg(new SubMsgHeader) } + + val isDownSendBusy = downRecParser.io.frameReq.ready + val isUpSendBusy = upRecParser.io.frameReq.ready + + val isDownSendPend = RegInit(false.B) + val isUpSendPend = RegInit(false.B) + + + //同时到来怎么办 + when( downRecParser.io.frameReq.fire ){ + when(downRecParser.io.frameReq.bits.frameStyle === FRAME_STYLE_PROBE){ //下行来了一个嗅探包 + isUpSendPend := true.B + downFrameInfo := downRecParser.io.frameReq.bits + println("Warning! No busy protection!") + } .elsewhen( downRecParser.io.frameReq.bits.frameStyle === FRAME_STYLE_COMMON ){ //下行来了一个普通包 + isDownSendPend := true.B + downFrameInfo := downRecParser.io.frameReq.bits + println("Warning! No busy protection!") + } + } .elsewhen( upRecParser.io.frameReq.fire ){ + when( upRecParser.io.frameReq.bits.frameStyle === FRAME_STYLE_PROBE){ //上行来了一个嗅探包 + println("Probe Resp!") + } .elsewhen( upRecParser.io.frameReq.bits.frameStyle === FRAME_STYLE_COMMON ){ //上行来了一个普通包 + isUpSendPend := true.B + upFrameInfo := upRecParser.io.frameReq.bits + println("Warning! No busy protection!") + } } - downStateNext := + val isDownSendProbe: Bool //下行探针 + val isUpSendProbe: Bool //上行探针 + val probeFrame: FrameHeader //固定化探针内容 + + downSendGen.io.frameReq.valid := + isDownSendPend | isDownSendProbe //下行转发 | 下行探针 + + assert( OneHot(isDownSendPend, isDownSendProbe) ) + + downSendGen.io.frameReq.bits := Mux1H(Seq( + isDownSendPend -> downFrameInfo, //下行转发 + isDownSendProbe -> probeFrame, //下行探针 + )) + + + when( downSendGen.io.frameReq.fire ){ + isDownSendPend := false.B + } + + upSendGen.io.frameReq.valid := + isUpSendPend | isUpSendProbe //上行转发 | 上行探针 + + assert( OneHot(isUpSendPend, isUpSendProbe) ) + + upSendGen.io.frameReq.bits := Mux1H(Seq( + isUpSendPend -> upFrameInfo, //上行转发 + isUpSendProbe -> probeFrame, //上行探针 + )) + + + when( upSendGen.io.frameReq.fire ){ + isUpSendPend := false.B + } + + when( downSendGen.io.frameReq.fire ){ + isDownSendPend := false.B + } + + + + + + + + + + + upSendFifo.io.enq.bits := Mux1H(Seq( + ( downRecParser.io.frameStyle === FRAME_STYLE_PROBE & downRecParser.io.stateCurr > STATE_HEADER ) -> downRecParser.io.data.bits //嗅探包 bypass到上行 + + + )) + + upSendFifo.io.enq.valid := + ((downRecParser.io.frameStyle === FRAME_STYLE_PROBE & downRecParser.io.stateCurr > STATE_HEADER ) & downRecParser.io.data.valid) | + + downRecParser.io.data.ready := + ((downRecParser.io.frameStyle === FRAME_STYLE_PROBE & downRecParser.io.stateCurr > STATE_HEADER ) & upSendFifo.io.enq.ready ) | + + + downSendFifo.io.enq.bits := Mux1H(Seq( + ( downRecParser.io.frameStyle === FRAME_STYLE_COMMON & downRecParser.io.stateCurr > STATE_HEADER ) -> + )) + + + + val isDownIdle + val isDownBypassToDown + val isDownWriteToSRAM + val isDownReadFromSRAM + val isDownLoopBack + + val isUpIdle + val isUpBypassToUp + val isUpWriteToSRAM + val isUpReadFromSRAM + val isUpBlackHole + + + + + + + + // val downOutFifo = Module(new Queue(UInt(8.W), 8)) + val upInFifo = Module(new Queue(UInt(8.W), 8)) + // val upOutFifo = Module(new Queue(UInt(8.W), 8)) + + + downInFifo.io.enq <> io.downIn + + io.downOut.valid := + ( === FRAME_STYLE_COMMON ) & + + io.upOut.valid := + ( === FRAME_STYLE_PROBE) & | + + io.upOut.bits := Mux1H(Seq( - //必须使用上升沿触发，以避免前一帧长度超过预期 - ( downStateCurr === STATE_IDLE ) -> Mux( ~RegNext(io.downIn.axis.valid) & io.downIn.axis.valid, STATE_HEADER, STATE_IDLE ), - ( downStateCurr === STATE_HEADER ) -> Mux( isShortRx, STATE_ERROR, - Mux( lengthCnt === 0, STATE_HEADER, - MuxCase( STATE_ERROR, Array( - ( io.downIn.axis.bits(1,0) === FRAME_STYLE_COMMON ) -> STATE_PAYLOAD_INDEX_STYLE, - ( io.downIn.axis.bits(1,0) === FRAME_STYLE_PROBE ) -> STATE_CRC, - )) - ) - ), - ( downStateCurr === STATE_PAYLOAD_INDEX_STYLE ) -> Mux( isShortRx, STATE_ERROR, - Mux( lengthCnt === 0, STATE_PAYLOAD_INDEX_STYLE, STATE_PAYLOAD_ADDR ) - ), - ( downStateCurr === STATE_PAYLOAD_ADDR ) -> Mux( isShortRx, STATE_ERROR, - Mux( lengthCnt === 0, STATE_PAYLOAD_ADDR, STATE_PAYLOAD_OP_LENGTH ) - ), - ( downStateCurr === STATE_PAYLOAD_OP_LENGTH ) -> Mux( isShortRx, STATE_ERROR, - Mux( lengthCnt === 0, STATE_PAYLOAD_OP_LENGTH, STATE_PAYLOAD_WORKCNT ) - ), - ( downStateCurr === STATE_PAYLOAD_WORKCNT ) -> Mux( isShortRx, STATE_ERROR, - Mux( lengthCnt === 0.U, STATE_PAYLOAD_WORKCNT, STATE_PAYLOAD_DATA ) - ), - ( downStateCurr === STATE_PAYLOAD_DATA ) -> Mux( isShortRx, STATE_ERROR, - Mux( lengthCnt === (subMsgLen - 1.U), - Mux(frameLenCnt === frameLenAim, STATE_CRC, STATE_PAYLOAD_INDEX_STYLE - ), STATE_PAYLOAD_DATA ) - ), - ( downStateCurr === STATE_CRC ) -> Mux( isShortRx, STATE_ERROR, - Mux( lengthCnt === (4 - 1).U, Mux( isCrcPass, STATE_IDLE, STATE_ERROR), STATE_CRC ) - ), - ( downStateCurr === STATE_ERROR ) -> Mux( isTxEnd, STATE_IDLE, STATE_ERROR ), + ( === FRAME_STYLE_PROBE) -> downInFifo.io.deq.bits, //嗅探包情形 + -> upInFifo.io.deq.bits, //上行 + -> //上行修正数据 )) + + io.downOut.bits := + Mux1H(Seq( + -> //自主发送嗅探包 + ( ) -> downInFifo.io.deq.bits, //下行 + ( ) -> //下行修正数据 + )) + + + + + downInFifo.io.deq.ready := + upInFifo.io.deq.ready := + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - // assert( ~(downStateCurr === STATE_HEADER & ~io.downIn.axis.fire), "Assert Failed!" ) - // assert( ~(downStateCurr === STATE_PAYLOAD_INDEX_STYLE & ~io.downIn.axis.fire), "Assert Failed!" ) - // assert( ~(downStateCurr === STATE_PAYLOAD_ADDR & ~io.downIn.axis.fire), "Assert Failed!" ) } diff --git a/src/main/scala/backBoard/shin/SlaveRecParser.scala b/src/main/scala/backBoard/shin/SlaveRecParser.scala new file mode 100644 index 0000000..7251c2a --- /dev/null +++ b/src/main/scala/backBoard/shin/SlaveRecParser.scala @@ -0,0 +1,151 @@ +package BACK + +import chisel3._ +import chisel3.util._ + + +class SlaveRecParserIO extends Module{ + val rec = Flipped( Decoupled(new AXIS_Bundle(8)) ) + + val data = Decoupled(UInt(8.W)) + + val stateNext = Output(UInt(4.W)) + val stateCurr = Output(UInt(4.W)) + + val frameReq = Valid( new Bundle{ + val frameLenAim = Output(UInt(12.W)) //帧长度目标 + val frameStyle = Output(UInt(2.W)) //包类型 + } ) + + val subMsgReq = Valid( new Bundle{ + val subMsg_devIndex = Output(UInt(14.W)) // 子报文中设备索引 + val subMsg_style = Output(UInt(2.W)) // 子报文类型 + val subMsg_address = Output(UInt(16.W)) //子报文地址 + val subMsg_operator = Output(UInt(4.W)) //子报文命令类型 + val subMsg_length = Output(UInt(12.W)) //子报文负载长度 + val subMsg_workCnt = Output(UInt(16.W)) //子报文工作计数 + ) + + + + +} + +class SlaveRecParser extends Module{ + val io: SlaveRecParserIO = IO(new SlaveRecParserIO) + + + + + val FRAME_STYLE_COMMON = 0.U + val FRAME_STYLE_PROBE = 1.U + + + val STATE_IDLE = 0.U //空闲 + val STATE_HEADER = 1.U //长度/ /保留2bits //包类型 + val STATE_PAYLOAD_INDEX_STYLE = 2.U //子报文设备索引 //子报文类型 + val STATE_PAYLOAD_ADDR = 3.U //子报文地址 + val STATE_PAYLOAD_OP_LENGTH = 4.U //子报文命令类型 //子报文长度 + val STATE_PAYLOAD_WORKCNT = 5.U //子报文工作计数 + val STATE_PAYLOAD_DATA = 6.U //子报文数据 + val STATE_CRC = 7.U //CRC校验 + val STATE_ERROR = 8.U // + val STATE_WAIT = 9.U + + + val stateNext = Wire(UInt(4.W)); io.stateNext := stateNext + val stateCurr = RegNext(stateNext, STATE_IDLE(4.W)); io.stateCurr := stateCurr + + val lengthCnt = Reg(UInt(11.W)) //动态计数器 + val frameLenCnt = Reg(UInt(12.W)) //帧长度计数 + val isCrcPass: Bool + val isTxEnd: Bool + val isShortRx: Bool //接收长度小于预期 + + + val frameLenAim = Reg(UInt(12.W)); io.frameLenAim := frameLenAim //帧长度目标 + val frameStyle = Reg(UInt(2.W)); io.frameStyle := frameStyle //包类型 + val subMsg_devIndex = Reg(UInt(14.W)); io.subMsg_devIndex := subMsg_devIndex // 子报文中设备索引 + val subMsg_style = Reg(UInt(2.W)); io.subMsg_style := subMsg_style // 子报文类型 + val subMsg_address = Reg(UInt(16.W)); io.subMsg_address := subMsg_address //子报文地址 + val subMsg_operator = Reg(UInt(4.W)); io.subMsg_operator := subMsg_operator //子报文命令类型 + val subMsg_length = Reg(UInt(12.W)); io.subMsg_length := subMsg_length //子报文负载长度 + val subMsg_workCnt = Reg(UInt(16.W)); io.subMsg_workCnt := subMsg_workCnt //子报文工作计数 + + + when( stateCurr === STATE_HEADER & lengthCnt === 0.U ){ + frameLenAim := io.rec.bits.tdata << 4 + } .elsewhen( stateCurr === STATE_HEADER & lengthCnt === 1.U ){ + frameLenAim := frameLenAim | io.rec.bits.tdata(7,4) + frameStyle := io.rec.bits.tdata(1,0) + } + + when( stateCurr === STATE_PAYLOAD_INDEX_STYLE & lengthCnt === 0.U ){ + subMsg_devIndex := io.rec.bits.tdata << 6 + } .elsewhen( stateCurr === STATE_PAYLOAD_INDEX_STYLE & lengthCnt === 1.U ){ + subMsg_devIndex := subMsg_devIndex | io.rec.bits.tdata(7,2) + subMsg_style := io.rec.bits.tdata(1,0) + } + + when( stateCurr === STATE_PAYLOAD_ADDR & lengthCnt === 0.U ){ + subMsg_address := io.rec.bits.tdata << 8 + } .elsewhen( stateCurr === STATE_PAYLOAD_ADDR & lengthCnt === 1.U ){ + subMsg_address := subMsg_address | io.rec.bits.tdata + } + + when( stateCurr === STATE_PAYLOAD_OP_LENGTH & lengthCnt === 0.U ){ + subMsg_operator := io.rec.bits.tdata(7,4) + subMsg_length := io.rec.bits.tdata(3,0) << 8 + } .elsewhen( stateCurr === STATE_PAYLOAD_OP_LENGTH & lengthCnt === 1.U ){ + subMsg_length := subMsg_length | io.rec.bits.tdata(7,0) + } + + when( stateCurr === STATE_PAYLOAD_WORKCNT & lengthCnt === 0.U ){ + subMsg_workCnt := io.rec.bits.tdata(7,0) << 8 + } .elsewhen( stateCurr === STATE_PAYLOAD_WORKCNT & lengthCnt === 1.U ){ + subMsg_workCnt := subMsg_workCnt | io.rec.bits.tdata(7,0) + } + + + stateNext := + Mux1H(Seq( + //必须使用上升沿触发，以避免前一帧长度超过预期 + ( stateCurr === STATE_IDLE ) -> Mux( ~RegNext(io.rec.valid) & io.rec.axis.valid, STATE_HEADER, STATE_IDLE ), + ( stateCurr === STATE_HEADER ) -> Mux( isShortRx, STATE_ERROR, + Mux( lengthCnt === 0, STATE_HEADER, + MuxCase( STATE_ERROR, Array( + ( io.rec.bits(1,0) === FRAME_STYLE_COMMON ) -> STATE_PAYLOAD_INDEX_STYLE, + ( io.rec.bits(1,0) === FRAME_STYLE_PROBE ) -> STATE_CRC, + )) + ) + ), + ( stateCurr === STATE_PAYLOAD_INDEX_STYLE ) -> Mux( isShortRx, STATE_ERROR, + Mux( lengthCnt === 0, STATE_PAYLOAD_INDEX_STYLE, STATE_PAYLOAD_ADDR ) + ), + ( stateCurr === STATE_PAYLOAD_ADDR ) -> Mux( isShortRx, STATE_ERROR, + Mux( lengthCnt === 0, STATE_PAYLOAD_ADDR, STATE_PAYLOAD_OP_LENGTH ) + ), + ( stateCurr === STATE_PAYLOAD_OP_LENGTH ) -> Mux( isShortRx, STATE_ERROR, + Mux( lengthCnt === 0, STATE_PAYLOAD_OP_LENGTH, STATE_PAYLOAD_WORKCNT ) + ), + ( stateCurr === STATE_PAYLOAD_WORKCNT ) -> Mux( isShortRx, STATE_ERROR, + Mux( lengthCnt === 0.U, STATE_PAYLOAD_WORKCNT, STATE_PAYLOAD_DATA ) + ), + ( stateCurr === STATE_PAYLOAD_DATA ) -> Mux( isShortRx, STATE_ERROR, + Mux( lengthCnt === ( subMsgLen - 1.U), + Mux( frameLenCnt === frameLenAim, STATE_CRC, STATE_PAYLOAD_INDEX_STYLE + ), STATE_PAYLOAD_DATA ) + ), + ( stateCurr === STATE_CRC ) -> Mux( isShortRx, STATE_ERROR, + Mux( lengthCnt === (4 - 1).U, Mux( isCrcPass, STATE_IDLE, STATE_ERROR), STATE_CRC ) + ), + ( stateCurr === STATE_ERROR ) -> Mux( isTxEnd, STATE_IDLE, STATE_ERROR ), + ( stateCurr === STATE_WAIT ) -> + )) + + + +} + + + diff --git a/src/main/scala/backBoard/shin/SlaveSendGen.scala b/src/main/scala/backBoard/shin/SlaveSendGen.scala new file mode 100644 index 0000000..5ca046e --- /dev/null +++ b/src/main/scala/backBoard/shin/SlaveSendGen.scala @@ -0,0 +1,146 @@ +package BACK + +import chisel3._ +import chisel3.util._ + + +class SubMsgTxInfo extends SubMsgHeader{ + val source = UInt(2.W) +} + + +class SlaveSendGenIO extends Bundle{ + + + val dataPing = Flipped( Decoupled(UInt(8.W)) ) + val dataPong = Flipped( Decoupled(UInt(8.W)) ) + val sram = + + // val stateNext = Output(UInt(4.W)) + // val stateCurr = Output(UInt(4.W)) + + + val frameReq = Flipped( Decoupled( new FrameHeader ) ) + + val subMsgReq = Flipped(Decoupled( new SubMsgHeader )) + + + + val send = Decoupled(new AXIS_Bundle(8)) + + +} + +class SlaveSendGen extends Module{ + val io: SlaveSendGenIO = IO(new SlaveSendGenIO) + + + val frameInfo = Reg(new FrameHeader) + + val subMsgInfoPing = Reg(new SubMsgHeader) + val subMsgInfoPong = Reg(new SubMsgHeader) + val isPingFill = RegInit(false.B) + val isPingEmit = RegInit(false.B) + + + when( io.frameReq.fire ){ + frameInfo := io.frameReq.bits + } + + when( io.subMsgReq.fire ){ + when( isPingFill ){ + subMsgInfoPing := io.subMsgReq.bits + } .otherwise{ + subMsgInfoPong := io.subMsgReq.bits + } + } + + val lengthCnt = Reg(UInt(12.W)) + + + + + val subMsgInfoSel = Mux( isPingEmit, subMsgInfoPing, subMsgInfoPong ) + + + + + + val STATE_IDLE = 0.U //空闲 + val STATE_FRAME_HEADER = 1.U //长度/ /保留2bits //包类型 + val STATE_SUBMSG_HEADER = 2.U + val STATE_SUBMSG_DATA = 3.U + val STATE_CRC = 4.U //CRC校验 + val STATE_ERROR = 5.U + val STATE_WAIT = 6.U + + + val stateNext = Wire(UInt(4.W)) + val stateCurr = RegNext(stateNext, STATE_IDLE(4.W)) + + stateNext := Mux1H(Seq( + (stateCurr === STATE_IDLE) -> Mux( io.frameReq.fire, STATE_FRAME_HEADER, STATE_IDLE ), + (stateCurr === STATE_FRAME_HEADER) -> Mux( lengthCnt === (2-1).U, Mux( io.subMsgReq.valid, STATE_SUBMSG_HEADER, STATE_ERROR ), STATE_FRAME_HEADER), + (stateCurr === STATE_SUBMSG_HEADER) -> Mux( lengthCnt === (64-1).U, STATE_SUBMSG_DATA, STATE_SUBMSG_HEADER), + (stateCurr === STATE_SUBMSG_DATA) -> + Mux( lengthCnt === subMsgInfoSel.subMsg_length-1.U, //已经发送完成该子报文 + Mux( frameLenCnt === frameInfo.lengthCnt, STATE_CRC, //主报文长度达到， 进CRC + Mux( io.subMsgReq.valid, STATE_SUBMSG_HEADER, STATE_ERROR ) ), //主报文长度未到，进下一个子报文 + STATE_SUBMSG_DATA + ), + (stateCurr === STATE_CRC) -> Mux( lengthCnt === (4-1).U, STATE_IDLE, STATE_CRC), + (stateCurr === STATE_ERROR) -> + (stateCurr === STATE_WAIT) -> + )) + + + io.send.valid := + (stateCurr === STATE_FRAME_HEADER) | + (stateCurr === STATE_SUBMSG_HEADER) | + (stateCurr === STATE_SUBMSG_DATA) | + (stateCurr === STATE_CRC) + + + val tdata_frame_header = Mux1H(Seq( + (lengthCnt === 0.U) -> frameLenAim(11,4), + (lengthCnt === 1.U) -> Cat( frameLenAim(3,0), 0.U(2.W), frameStyle), + )) + + val tdata_submsg_header = Mux1H(Seq( + (lengthCnt === 0.U) -> subMsgInfoSel.subMsg_devIndex(13,6), + (lengthCnt === 1.U) -> Cat( subMsgInfoSel.subMsg_devIndex(5,0), subMsgInfoSel.subMsg_style), + (lengthCnt === 2.U) -> subMsgInfoSel.subMsg_address(15,8), + (lengthCnt === 3.U) -> subMsgInfoSel.subMsg_address(7,0), + (lengthCnt === 4.U) -> Cat(subMsgInfoSel.subMsg_operator, subMsgInfoSel.subMsg_length(11,8)), + (lengthCnt === 5.U) -> subMsgInfoSel.subMsg_length(7,0), + (lengthCnt === 6.U) -> subMsgInfoSel.subMsg_workCnt(15,8), + (lengthCnt === 7.U) -> subMsgInfoSel.subMsg_workCnt(7,0), + )) + + val tdata_submsg_data = Mux1H(Seq( + (subMsgInfoSel.source === 0.U) -> dataPing.bits + (subMsgInfoSel.source === 1.U) -> dataPong.bits + (subMsgInfoSel.source === 2.U) -> sram.rdata + )) + + dataPing.ready := + dataPong.ready := + sram.enr := + + val tdata_crc = Mux1H(Seq( + + )) + + io.send.bits.tdata := Mux1H(Seq( + (stateCurr === STATE_FRAME_HEADER) -> tdata_frame_header, + (stateCurr === STATE_SUBMSG_HEADER) -> tdata_submsg_header, + (stateCurr === STATE_SUBMSG_DATA) -> tdata_submsg_data, + (stateCurr === STATE_CRC) -> tdata_crc, + )) + + io.send.bits.tuser := + io.send.bits.tlast := + + + +} \ No newline at end of file