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RuigeLee
2024-05-21 15:52:49 +08:00
parent fa45f0fabc
commit e1f72eaaeb
1 changed files with 4 additions and 4 deletions
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8
src/main/scala/backBoard/BackBoardMst.scala
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@@ -617,14 +617,14 @@ with BackBoardMstLVDSError{
mirrorDown.io.enwB := false.B mirrorDown.io.enwB := false.B
mirrorDown.io.datawB := 0.U mirrorDown.io.datawB := 0.U
mirrorDown.io.enrB := (stateCur === 4.U || stateCur === 5.U) & (ctrlTransmit | ctrlUnicast) mirrorDown.io.enrB := (stateCur === 4.U || stateCur === 5.U) & (ctrlTransmit | ctrlUnicast)
io.lvdsMst.tx_data_in := Mux( addrr.extract(0), mirrorDown.io.datarB(15,8), mirrorDown.io.datarB(7,0) ) io.lvdsMst.tx_data_in := Mux( addrr.extract(0), mirrorDown.io.datarB(7,0), mirrorDown.io.datarB(15,8) )
mirrorDown.io.addrB := addrr >> 1 mirrorDown.io.addrB := addrr >> 1
val rxData_msb = RegEnable( io.lvdsMst.rx_data_out, io.lvdsMst.rx_data_valid & (ctrlTransmit | ctrlUnicast) & ~addrw.extract(0) ) val rxData_lsb = RegEnable( io.lvdsMst.rx_data_out, io.lvdsMst.rx_data_valid & (ctrlTransmit | ctrlUnicast) & ~addrw.extract(0) )
mirrorUp.io.enrB := false.B mirrorUp.io.enrB := false.B
mirrorUp.io.enwB := io.lvdsMst.rx_data_valid & (ctrlTransmit | ctrlUnicast) & addrw.extract(0) mirrorUp.io.enwB := io.lvdsMst.rx_data_valid & (ctrlTransmit | ctrlUnicast) & addrw.extract(0)
mirrorUp.io.datawB := (rxData_msb << 8) | io.lvdsMst.rx_data_out mirrorUp.io.datawB := Cat( io.lvdsMst.rx_data_out, rxData_lsb )
mirrorUp.io.addrB := addrw >> 1 mirrorUp.io.addrB := addrw >> 1
} }