From e1f72eaaeb88075dd30acd9bac7a8bd7a3cb4ae2 Mon Sep 17 00:00:00 2001 From: RuigeLee Date: Tue, 21 May 2024 15:52:49 +0800 Subject: [PATCH] =?UTF-8?q?=E5=A4=A7=E5=B0=8F=E7=AB=AF=E4=BA=89=E8=AE=AE?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- src/main/scala/backBoard/BackBoardMst.scala | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/main/scala/backBoard/BackBoardMst.scala b/src/main/scala/backBoard/BackBoardMst.scala index e133706..c0283ed 100644 --- a/src/main/scala/backBoard/BackBoardMst.scala +++ b/src/main/scala/backBoard/BackBoardMst.scala @@ -617,14 +617,14 @@ with BackBoardMstLVDSError{ mirrorDown.io.enwB := false.B mirrorDown.io.datawB := 0.U mirrorDown.io.enrB := (stateCur === 4.U || stateCur === 5.U) & (ctrlTransmit | ctrlUnicast) - io.lvdsMst.tx_data_in := Mux( addrr.extract(0), mirrorDown.io.datarB(15,8), mirrorDown.io.datarB(7,0) ) + io.lvdsMst.tx_data_in := Mux( addrr.extract(0), mirrorDown.io.datarB(7,0), mirrorDown.io.datarB(15,8) ) mirrorDown.io.addrB := addrr >> 1 - val rxData_msb = RegEnable( io.lvdsMst.rx_data_out, io.lvdsMst.rx_data_valid & (ctrlTransmit | ctrlUnicast) & ~addrw.extract(0) ) + val rxData_lsb = RegEnable( io.lvdsMst.rx_data_out, io.lvdsMst.rx_data_valid & (ctrlTransmit | ctrlUnicast) & ~addrw.extract(0) ) mirrorUp.io.enrB := false.B mirrorUp.io.enwB := io.lvdsMst.rx_data_valid & (ctrlTransmit | ctrlUnicast) & addrw.extract(0) - mirrorUp.io.datawB := (rxData_msb << 8) | io.lvdsMst.rx_data_out - mirrorUp.io.addrB := addrw >> 1 + mirrorUp.io.datawB := Cat( io.lvdsMst.rx_data_out, rxData_lsb ) + mirrorUp.io.addrB := addrw >> 1 }