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This commit is contained in:
Ruige Lee
2025-04-24 17:31:44 +08:00
parent 4013e19eda
commit dc67286e23
8 changed files with 259 additions and 236 deletions
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31
src/main/scala/backBoard/shin/SlaveParser.scala
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@@ -76,6 +76,9 @@ abstract class SlaveParserBase extends Module{
val downSendGen = Module(new SlaveSendGen)
val upSendGen = Module(new SlaveSendGen)
val isReadyToProbe = RegInit(false.B)
val isLastDevice: Bool = RegInit(false.B)
val isDeviceModified: Bool = RegInit(true.B)
val localDevIndex = RegInit(0.U(14.W)) //当前设备索引
dontTouch(localDevIndex)
@@ -141,7 +144,7 @@ abstract class SlaveParserBase extends Module{
isUpSendPend & upRecParser.io.subMsgReq.fire | //上行转发
isReadyToProbe // 上行探针
assert( ~(isUpSendPend & isUpSendProbe), "Assert Failed, Check Softwave, Probe is Sent while transfering!\n" )
assert( ~(isUpSendPend & isReadyToProbe), "Assert Failed, Check Softwave, Probe is Sent while transfering!\n" )
upSendGen.io.frameReq.bits := Mux1H(Seq(
isUpSendPend -> upFrameInfo, //上行转发
@@ -428,14 +431,7 @@ trait SlaveParserRW{ this: SlaveParserBase =>
io.dSMenq(0) := isWrite & isWRSM0 & io.trigAddr(0) === addrw(10,0)
io.uSMdeq(1) := isRead & isRDSM1 & io.trigAddr(1) === readSMAddr(10,0)
io.dSMenq(2) := isWrite & isWRSM2 & io.trigAddr(2) === addrw(10,0)
io.uSMdeq(3) := isRead & isRDSM3 & io.trigAddr(3) === readSMAddr(10,0)
io.dSMenq(4) := isWrite & isWRSM4 & io.trigAddr(4) === addrw(10,0)
io.uSMdeq(5) := isRead & isRDSM5 & io.trigAddr(5) === readSMAddr(10,0)
io.dSMenq(6) := isWrite & isWRSM6 & io.trigAddr(6) === addrw(10,0)
io.uSMdeq(7) := isRead & isRDSM7 & io.trigAddr(7) === readSMAddr(10,0)
@@ -519,6 +515,18 @@ trait SlaveParserRW{ this: SlaveParserBase =>
io.sram_r(1).addrr := readSMAddr(10,0)
io.sram_r(2).addrr := readSMAddr(10,0)
io.sram_r(3).addrr := readSMAddr(10,0)
io.dSMenq(0) := isWrite & isWRSM0 & io.trigAddr(0) === addrw(10,0)
io.uSMdeq(0) := isRead & isRDSM1 & io.trigAddr(1) === readSMAddr(10,0)
io.dSMenq(1) := isWrite & isWRSM2 & io.trigAddr(2) === addrw(10,0)
io.uSMdeq(1) := isRead & isRDSM3 & io.trigAddr(3) === readSMAddr(10,0)
io.dSMenq(2) := isWrite & isWRSM4 & io.trigAddr(4) === addrw(10,0)
io.uSMdeq(2) := isRead & isRDSM5 & io.trigAddr(5) === readSMAddr(10,0)
io.dSMenq(3) := isWrite & isWRSM6 & io.trigAddr(6) === addrw(10,0)
io.uSMdeq(3) := isRead & isRDSM7 & io.trigAddr(7) === readSMAddr(10,0)
}
@@ -618,7 +626,7 @@ trait SlaveParserProbe{ this: SlaveParserBase =>
val isReadyToProbe = RegInit(false.B)
when( downRecParser.io.frameReq.fire & downRecParser.io.frameReq.bits.frameStyle === FRAME_STYLE_PROBE ){ //下行来了一个嗅探包
isReadyToProbe := true.B
@@ -634,8 +642,7 @@ trait SlaveParserProbe{ this: SlaveParserBase =>
val isLastDevice: Bool = RegInit(false.B)
val isDeviceModified: Bool = RegInit(true.B)
when( upRecParser.io.frameReq.fire & upRecParser.io.frameReq.bits.frameStyle === FRAME_STYLE_PROBE ){ //上行来了一个嗅探包
probeRecCnt := 0.U