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从站编译完成

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This commit is contained in:
Ruige Lee
2025-04-24 17:31:44 +08:00
parent 4013e19eda
commit dc67286e23
8 changed files with 259 additions and 236 deletions
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71
src/main/scala/backBoard/shin/ShinTop.scala
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@@ -25,15 +25,21 @@ class ShinTopIO extends Bundle{
val timeStamp = Input(UInt(64.W))
val dSMdeq = Input( Vec(4, Bool()) )
val uSMenq = Input( Vec(4, Bool()) )
val sram_w = Vec( 4, new SRAM2kWRIO) //QSPI
val sram_r = Vec( 4, new SRAM2kRDIO) //QSPI
val sram = MixedVec(
Vec(4, new SRAM2kIO)
Vec(4, new SRAM2kIO)
Vec(4, new SRAM2kIO)
Vec(4, new SRAM2kIO)
Vec(2, new SRAM2kIO)
Vec(2, new SRAM2kIO)
Vec(2, new SRAM2kIO)
Vec(2, new SRAM2kIO)
Flipped(Vec(4, new SRAM2kIO)),
Flipped(Vec(4, new SRAM2kIO)),
Flipped(Vec(4, new SRAM2kIO)),
Flipped(Vec(4, new SRAM2kIO)),
Flipped(Vec(2, new SRAM2kIO)),
Flipped(Vec(2, new SRAM2kIO)),
Flipped(Vec(2, new SRAM2kIO)),
Flipped(Vec(2, new SRAM2kIO)),
)
}
@@ -46,18 +52,18 @@ class ShinTop extends Module{
// val CDROut = for( i <- 0 until 2 ) yield { Module(new CDROut) }
val slaveParser = Module(new SlaveParser )
val masterParser = Module(new MasterParser)
// val masterParser = Module(new MasterParser)
val smUnit = Seq(
Module( new SMUnit(depth = 4) )
Module( new SMUnit(depth = 4) )
Module( new SMUnit(depth = 4) )
Module( new SMUnit(depth = 4) )
Module( new SMUnit(depth = 2) )
Module( new SMUnit(depth = 2) )
Module( new SMUnit(depth = 2) )
Module( new SMUnit(depth = 2) )
Module( new SMUnit(depth = 4) ),
Module( new SMUnit(depth = 4) ),
Module( new SMUnit(depth = 4) ),
Module( new SMUnit(depth = 4) ),
Module( new SMUnit(depth = 2) ),
Module( new SMUnit(depth = 2) ),
Module( new SMUnit(depth = 2) ),
Module( new SMUnit(depth = 2) ),
)
@@ -66,16 +72,38 @@ class ShinTop extends Module{
smUnit(4).io.sram_w := slaveParser.io.sram_w(2)
smUnit(6).io.sram_w := slaveParser.io.sram_w(3)
smUnit(0).io.sram_r <> io.sram_r(0)
smUnit(2).io.sram_r <> io.sram_r(1)
smUnit(4).io.sram_r <> io.sram_r(2)
smUnit(6).io.sram_r <> io.sram_r(3)
smUnit(1).io.sram_r <> slaveParser.io.sram_r(0)
smUnit(3).io.sram_r <> slaveParser.io.sram_r(1)
smUnit(5).io.sram_r <> slaveParser.io.sram_r(2)
smUnit(7).io.sram_r <> slaveParser.io.sram_r(3)
smUnit(1).io.sram_w := io.sram_w(0)
smUnit(3).io.sram_w := io.sram_w(1)
smUnit(5).io.sram_w := io.sram_w(2)
smUnit(7).io.sram_w := io.sram_w(3)
smUnit(0).io.enq := slaveParser.io.dSMenq(0)
smUnit(2).io.enq := slaveParser.io.dSMenq(1)
smUnit(4).io.enq := slaveParser.io.dSMenq(2)
smUnit(6).io.enq := slaveParser.io.dSMenq(3)
smUnit(0).io.deq := io.dSMdeq(0)
smUnit(2).io.deq := io.dSMdeq(1)
smUnit(4).io.deq := io.dSMdeq(2)
smUnit(6).io.deq := io.dSMdeq(3)
smUnit(1).io.enq := io.uSMenq(0)
smUnit(3).io.enq := io.uSMenq(1)
smUnit(5).io.enq := io.uSMenq(2)
smUnit(7).io.enq := io.uSMenq(3)
smUnit(1).io.deq := slaveParser.io.uSMdeq(0)
smUnit(3).io.deq := slaveParser.io.uSMdeq(1)
smUnit(5).io.deq := slaveParser.io.uSMdeq(2)
@@ -99,7 +127,14 @@ class ShinTop extends Module{
slaveParser.io.timeStamp := io.timeStamp
slaveParser.io.trigAddr(0) := "hffff".U
slaveParser.io.trigAddr(1) := "hffff".U
slaveParser.io.trigAddr(2) := "hffff".U
slaveParser.io.trigAddr(3) := "hffff".U
slaveParser.io.trigAddr(4) := "hffff".U
slaveParser.io.trigAddr(5) := "hffff".U
slaveParser.io.trigAddr(6) := "hffff".U
slaveParser.io.trigAddr(7) := "hffff".U