从站编译完成

src/main/scala/backBoard/shin/SRAMFifo.scala

@@ -3,23 +3,7 @@ package BACK
 import chisel3._
 import chisel3.util._
 
-class SRAM2kWRIO extends Bundle {
-  val addrw = Input(UInt(11.W))
-  val dataw = Input( UInt(8.W) )
-  val enw   = Input(Bool())
-}
 
-class SRAM2kRDIO extends Bundle {
-  val addrr = Input(UInt(11.W))
-  val datar = Output( UInt(8.W) )
-  val enr   = Input(Bool())
-}
-
-
-class SRAM2kIO extends Bundle {
-  val rd = new SRAM2kRDIO
-  val wr = new SRAM2kWRIO
-}
 
 // class SRAM2kFifoIO extends Bundle {
 //   val sram = new SRAM2kIO