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从站编译完成

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This commit is contained in:
Ruige Lee
2025-04-24 17:31:44 +08:00
parent 4013e19eda
commit dc67286e23
8 changed files with 259 additions and 236 deletions
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128
src/main/scala/backBoard/shin/MasterParser.scala
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@@ -1,90 +1,90 @@
package BACK
// package BACK
import chisel3._
import chisel3.util._
// import chisel3._
// import chisel3.util._
class MasterParserIO extends Module{
val downOut = Decoupled(new AXIS_Bundle(8))
val upIn = Flipped( Decoupled(new AXIS_Bundle(8)) )
// class MasterParserIO extends Module{
// val downOut = Decoupled(new AXIS_Bundle(8))
// val upIn = Flipped( Decoupled(new AXIS_Bundle(8)) )
val sram_r = Flipped(new ShareSRAMIO)
val sram_w = Flipped(new ShareSRAMIO)
// val sram_r = Flipped(new ShareSRAMIO)
// val sram_w = Flipped(new ShareSRAMIO)
val req = Valid(new Bundle{
val length = UInt(12.W)
})
val rsp = Valid(new Bundle{
val isError = Bool()
val length = UInt(12.W)
})
// val req = Valid(new Bundle{
// val length = UInt(12.W)
// })
// val rsp = Valid(new Bundle{
// val isError = Bool()
// val length = UInt(12.W)
// })
}
// }
abstract class MasterParserBase extends Module{
val io: MasterParserIO = IO(new MasterParserIO)
// abstract class MasterParserBase extends Module{
// val io: MasterParserIO = IO(new MasterParserIO)
val sendCnt = Reg(UInt(11.W))
val sendLen = Reg(UInt(11.W))
// val sendCnt = Reg(UInt(11.W))
// val sendLen = Reg(UInt(11.W))
val reqReady = RegInit(true.B)
val sendAddr = Reg(UInt(12.W))
// val reqReady = RegInit(true.B)
// val sendAddr = Reg(UInt(12.W))
io.req.ready := reqReady
// io.req.ready := reqReady
when( io.req.fire ){
reqReady := false.B
} .elsewhen( io.downOut.fire & sendCnt === sendLen ){
reqReady := true.B
}
// when( io.req.fire ){
// reqReady := false.B
// } .elsewhen( io.downOut.fire & sendCnt === sendLen ){
// reqReady := true.B
// }
when( io.req.fire ){
sendLen := io.req.bits.length
sendCnt := 0.U
} .elsewhen( io.downOut.fire ){
sendCnt := sendCnt + 1.U
}
// when( io.req.fire ){
// sendLen := io.req.bits.length
// sendCnt := 0.U
// } .elsewhen( io.downOut.fire ){
// sendCnt := sendCnt + 1.U
// }
when( reqReady ){
sendAddr := 0.U
} .elsewhen( io.downOut.fire ){
sendAddr := sendAddr + 1.U
}
// when( reqReady ){
// sendAddr := 0.U
// } .elsewhen( io.downOut.fire ){
// sendAddr := sendAddr + 1.U
// }
io.sram_r.enr :=
io.req.fire | io.downOut.fire
// io.sram_r.enr :=
// io.req.fire | io.downOut.fire
io.sram_r.addr := Mux( io.req.fire, io.req.bits.addr, sendCnt )
// io.sram_r.addr := Mux( io.req.fire, io.req.bits.addr, sendCnt )
io.downOut.valid := ~reqReady
io.downOut.bits.tdata := io.req.bits.datar
io.downOut.bits.tuser := false.B
io.downOut.bits.tlast := sendCnt === sendLen
// io.downOut.valid := ~reqReady
// io.downOut.bits.tdata := io.req.bits.datar
// io.downOut.bits.tuser := false.B
// io.downOut.bits.tlast := sendCnt === sendLen
val recAddr = Reg(UInt(12.W))
// val recAddr = Reg(UInt(12.W))
io.upIn.ready := true.B
// io.upIn.ready := true.B
io.sram_w.enw := io.upIn.fire
io.sram_w.addr := recAddr
io.sram_w.dataw := io.upIn.bits.tdata
// io.sram_w.enw := io.upIn.fire
// io.sram_w.addr := recAddr
// io.sram_w.dataw := io.upIn.bits.tdata
when( io.upIn.fire ){
when( io.upIn.bits.tlast ){
recAddr := 0.U
} .otherwise{
recAddr := recAddr + 1.U
}
}
// when( io.upIn.fire ){
// when( io.upIn.bits.tlast ){
// recAddr := 0.U
// } .otherwise{
// recAddr := recAddr + 1.U
// }
// }
io.rsp.valid := io.upIn.fire & io.upIn.bits.tlast
io.rsp.bits.isError := io.upIn.fire & io.upIn.bits.tuser
io.rsp.bits.length := recAddr
// io.rsp.valid := io.upIn.fire & io.upIn.bits.tlast
// io.rsp.bits.isError := io.upIn.fire & io.upIn.bits.tuser
// io.rsp.bits.length := recAddr
@@ -92,9 +92,9 @@ abstract class MasterParserBase extends Module{
}
// }
class MasterParser extends MasterParserBase{
// class MasterParser extends MasterParserBase{
}
// }