移除4b5b特性，只使用8b10b特性

src/main/scala/backBoard/shin/Interface.scala

@@ -45,7 +45,6 @@ class CommonRegisterBundle extends Bundle{
   val uniCode = UInt(64.W)
 
   val dwupEx   = Bool()
-  val b8b4Sel  = Bool()
   val cdrParam = UInt(8.W)
 
 
@@ -285,7 +284,6 @@ abstract class InterfaceBase extends Module with RequireAsyncReset{
 
       Seq(
         (addr === "h4a".U ) -> cReg.dwupEx,
-        (addr === "h4c".U ) -> cReg.b8b4Sel,
         (addr === "h4e".U ) -> cReg.cdrParam,
 
         (addr === "h70".U ) -> cReg.intEnable(7,0),
@@ -1049,9 +1047,6 @@ trait InterfaceSystem{ this: InterfaceBase =>
   val dwupExTemp = RegEnable(dataw, 0.U(8.W), isEnW & addrw === "h4a".U )
   cReg.dwupEx   := RegEnable(dwupExTemp, 0.U(8.W), isEnW & addrw === "h4b".U & dataw === "h58".U )
 
-  val b8b4SelTemp = RegEnable(dataw, 0.U(8.W), isEnW & addrw === "h4c".U )
-  cReg.b8b4Sel  := RegEnable(b8b4SelTemp, 0.U(8.W), isEnW & addrw === "h4d".U & dataw === "h59".U )
-
   val cdrParamTemp = RegEnable(dataw, 0.U(8.W), isEnW & addrw === "h4e".U )
   cReg.cdrParam := RegEnable(cdrParamTemp, 0.U(8.W), isEnW & addrw === "h4f".U & dataw === "h60".U )
 

src/main/scala/backBoard/shin/MstSlvSwitch.scala

@@ -54,11 +54,6 @@ abstract class MstSlvSwitchBase extends Module with RequireAsyncReset{
   val slaveParser  = Module(new SlaveParser )
   val masterParser = Module(new MasterParser)
 
-  val b4b5DownEncoder = Module(new b4b5DualEncode)
-  val b4b5DownDecoder = Module(new b4b5DualDecode)
-  val b4b5UpEncoder = Module(new b4b5DualEncode)
-  val b4b5UpDecoder = Module(new b4b5DualDecode)
-
   val b8b10DownEncoder = Module(new b8b10Encode)
   val b8b10DownDecoder = Module(new b8b10Decode)
   val b8b10UpEncoder = Module(new b8b10Encode)
@@ -211,7 +206,10 @@ abstract class MstSlvSwitchBase extends Module with RequireAsyncReset{
     }    
   }
 
-
+  b8b10DownEncoder.io <> downCDROut.io.encode
+  b8b10DownDecoder.io <> downCDRInAxis.io.decode
+  b8b10UpEncoder.io   <> upCDROut.io.encode
+  b8b10UpDecoder.io   <> upCDRInAxis.io.decode
 
 
   //default
@@ -573,36 +571,6 @@ trait MstSlvSwitchDataPath{ this: MstSlvSwitchBase =>
   }
 }
 
-trait MstSlvSwitchB8B4{ this: MstSlvSwitchBase =>
-  val isUsing8b10b = ~interface.io.cReg.b8b4Sel.extract(0)
-
-  when( isUsing8b10b ){
-    b8b10DownEncoder.io <> downCDROut.io.encode
-    b8b10DownDecoder.io <> downCDRInAxis.io.decode
-    b8b10UpEncoder.io   <> upCDROut.io.encode
-    b8b10UpDecoder.io   <> upCDRInAxis.io.decode
-
-    b4b5DownEncoder.io.isEnable := false.B
-    b4b5DownEncoder.io.dataIn := 0.U
-    b4b5DownDecoder.io.dataIn := 0.U
-    b4b5UpEncoder.io.isEnable := false.B
-    b4b5UpEncoder.io.dataIn := 0.U
-    b4b5UpDecoder.io.dataIn := 0.U
-  } .otherwise{
-    b4b5DownEncoder.io <> downCDROut.io.encode
-    b4b5DownDecoder.io <> downCDRInAxis.io.decode
-    b4b5UpEncoder.io <> upCDROut.io.encode
-    b4b5UpDecoder.io <> upCDRInAxis.io.decode
-
-    b8b10DownEncoder.io.isEnable := false.B
-    b8b10DownEncoder.io.dataIn := 0.U
-    b8b10DownDecoder.io.dataIn := 0.U
-    b8b10UpEncoder.io.isEnable := false.B
-    b8b10UpEncoder.io.dataIn := 0.U
-    b8b10UpDecoder.io.dataIn := 0.U
-  }
-}
-
 trait MstSlvSwitchCDRIn{ this: MstSlvSwitchBase =>
   val cdrSelB = interface.io.cReg.cdrParam === 1.U
   val cdrSelC = interface.io.cReg.cdrParam === 2.U
@@ -649,7 +617,6 @@ with MstSlvSwitchMaster
 with MstSlvSwitchSlave
 with MstSlvSwitchWatchDog
 with MstSlvSwitchDataPath
-with MstSlvSwitchB8B4
 with MstSlvSwitchCDRIn{