From db2e84c7f5d16d87cd9912bd9ed6b8304ab0daf3 Mon Sep 17 00:00:00 2001 From: RuigeLee Date: Tue, 28 Jul 2026 16:09:20 +0800 Subject: [PATCH] =?UTF-8?q?=E7=A7=BB=E9=99=A44b5b=E7=89=B9=E6=80=A7?= =?UTF-8?q?=EF=BC=8C=E5=8F=AA=E4=BD=BF=E7=94=A88b10b=E7=89=B9=E6=80=A7?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- src/main/scala/backBoard/shin/Interface.scala | 5 - .../scala/backBoard/shin/MstSlvSwitch.scala | 41 +---- .../shin/{b4b5.scala => b4b5.scala.bk} | 156 +++++++++--------- 3 files changed, 82 insertions(+), 120 deletions(-) rename src/main/scala/backBoard/shin/{b4b5.scala => b4b5.scala.bk} (96%) diff --git a/src/main/scala/backBoard/shin/Interface.scala b/src/main/scala/backBoard/shin/Interface.scala index 58671b2..aeeee03 100644 --- a/src/main/scala/backBoard/shin/Interface.scala +++ b/src/main/scala/backBoard/shin/Interface.scala @@ -45,7 +45,6 @@ class CommonRegisterBundle extends Bundle{ val uniCode = UInt(64.W) val dwupEx = Bool() - val b8b4Sel = Bool() val cdrParam = UInt(8.W) @@ -285,7 +284,6 @@ abstract class InterfaceBase extends Module with RequireAsyncReset{ Seq( (addr === "h4a".U ) -> cReg.dwupEx, - (addr === "h4c".U ) -> cReg.b8b4Sel, (addr === "h4e".U ) -> cReg.cdrParam, (addr === "h70".U ) -> cReg.intEnable(7,0), @@ -1049,9 +1047,6 @@ trait InterfaceSystem{ this: InterfaceBase => val dwupExTemp = RegEnable(dataw, 0.U(8.W), isEnW & addrw === "h4a".U ) cReg.dwupEx := RegEnable(dwupExTemp, 0.U(8.W), isEnW & addrw === "h4b".U & dataw === "h58".U ) - val b8b4SelTemp = RegEnable(dataw, 0.U(8.W), isEnW & addrw === "h4c".U ) - cReg.b8b4Sel := RegEnable(b8b4SelTemp, 0.U(8.W), isEnW & addrw === "h4d".U & dataw === "h59".U ) - val cdrParamTemp = RegEnable(dataw, 0.U(8.W), isEnW & addrw === "h4e".U ) cReg.cdrParam := RegEnable(cdrParamTemp, 0.U(8.W), isEnW & addrw === "h4f".U & dataw === "h60".U ) diff --git a/src/main/scala/backBoard/shin/MstSlvSwitch.scala b/src/main/scala/backBoard/shin/MstSlvSwitch.scala index 0a9d7d8..28b8a11 100644 --- a/src/main/scala/backBoard/shin/MstSlvSwitch.scala +++ b/src/main/scala/backBoard/shin/MstSlvSwitch.scala @@ -54,11 +54,6 @@ abstract class MstSlvSwitchBase extends Module with RequireAsyncReset{ val slaveParser = Module(new SlaveParser ) val masterParser = Module(new MasterParser) - val b4b5DownEncoder = Module(new b4b5DualEncode) - val b4b5DownDecoder = Module(new b4b5DualDecode) - val b4b5UpEncoder = Module(new b4b5DualEncode) - val b4b5UpDecoder = Module(new b4b5DualDecode) - val b8b10DownEncoder = Module(new b8b10Encode) val b8b10DownDecoder = Module(new b8b10Decode) val b8b10UpEncoder = Module(new b8b10Encode) @@ -211,7 +206,10 @@ abstract class MstSlvSwitchBase extends Module with RequireAsyncReset{ } } - + b8b10DownEncoder.io <> downCDROut.io.encode + b8b10DownDecoder.io <> downCDRInAxis.io.decode + b8b10UpEncoder.io <> upCDROut.io.encode + b8b10UpDecoder.io <> upCDRInAxis.io.decode //default @@ -573,36 +571,6 @@ trait MstSlvSwitchDataPath{ this: MstSlvSwitchBase => } } -trait MstSlvSwitchB8B4{ this: MstSlvSwitchBase => - val isUsing8b10b = ~interface.io.cReg.b8b4Sel.extract(0) - - when( isUsing8b10b ){ - b8b10DownEncoder.io <> downCDROut.io.encode - b8b10DownDecoder.io <> downCDRInAxis.io.decode - b8b10UpEncoder.io <> upCDROut.io.encode - b8b10UpDecoder.io <> upCDRInAxis.io.decode - - b4b5DownEncoder.io.isEnable := false.B - b4b5DownEncoder.io.dataIn := 0.U - b4b5DownDecoder.io.dataIn := 0.U - b4b5UpEncoder.io.isEnable := false.B - b4b5UpEncoder.io.dataIn := 0.U - b4b5UpDecoder.io.dataIn := 0.U - } .otherwise{ - b4b5DownEncoder.io <> downCDROut.io.encode - b4b5DownDecoder.io <> downCDRInAxis.io.decode - b4b5UpEncoder.io <> upCDROut.io.encode - b4b5UpDecoder.io <> upCDRInAxis.io.decode - - b8b10DownEncoder.io.isEnable := false.B - b8b10DownEncoder.io.dataIn := 0.U - b8b10DownDecoder.io.dataIn := 0.U - b8b10UpEncoder.io.isEnable := false.B - b8b10UpEncoder.io.dataIn := 0.U - b8b10UpDecoder.io.dataIn := 0.U - } -} - trait MstSlvSwitchCDRIn{ this: MstSlvSwitchBase => val cdrSelB = interface.io.cReg.cdrParam === 1.U val cdrSelC = interface.io.cReg.cdrParam === 2.U @@ -649,7 +617,6 @@ with MstSlvSwitchMaster with MstSlvSwitchSlave with MstSlvSwitchWatchDog with MstSlvSwitchDataPath -with MstSlvSwitchB8B4 with MstSlvSwitchCDRIn{ diff --git a/src/main/scala/backBoard/shin/b4b5.scala b/src/main/scala/backBoard/shin/b4b5.scala.bk similarity index 96% rename from src/main/scala/backBoard/shin/b4b5.scala rename to src/main/scala/backBoard/shin/b4b5.scala.bk index 4283cba..6540bc3 100644 --- a/src/main/scala/backBoard/shin/b4b5.scala +++ b/src/main/scala/backBoard/shin/b4b5.scala.bk @@ -1,78 +1,78 @@ -package BACK - -import chisel3._ -import chisel3.util._ - - -object b4b5Encoder{ - def apply( enq: UInt ): UInt = { - Mux1H(Seq( - (enq === "b0000".U) -> "b11110".U(5.W), - (enq === "b0001".U) -> "b01001".U(5.W), - (enq === "b0010".U) -> "b10100".U(5.W), - (enq === "b0011".U) -> "b10101".U(5.W), - (enq === "b0100".U) -> "b01010".U(5.W), - (enq === "b0101".U) -> "b01011".U(5.W), - (enq === "b0110".U) -> "b01110".U(5.W), - (enq === "b0111".U) -> "b01111".U(5.W), - (enq === "b1000".U) -> "b10010".U(5.W), - (enq === "b1001".U) -> "b10011".U(5.W), - (enq === "b1010".U) -> "b10110".U(5.W), - (enq === "b1011".U) -> "b10111".U(5.W), - (enq === "b1100".U) -> "b11010".U(5.W), - (enq === "b1101".U) -> "b11011".U(5.W), - (enq === "b1110".U) -> "b11100".U(5.W), - (enq === "b1111".U) -> "b11101".U(5.W), - )) - } -} - -object b4b5Decoder{ - def apply( enq: UInt ): UInt = { - Mux1H(Seq( - (enq === "b11110".U) -> "b0000".U(4.W), - (enq === "b01001".U) -> "b0001".U(4.W), - (enq === "b10100".U) -> "b0010".U(4.W), - (enq === "b10101".U) -> "b0011".U(4.W), - (enq === "b01010".U) -> "b0100".U(4.W), - (enq === "b01011".U) -> "b0101".U(4.W), - (enq === "b01110".U) -> "b0110".U(4.W), - (enq === "b01111".U) -> "b0111".U(4.W), - (enq === "b10010".U) -> "b1000".U(4.W), - (enq === "b10011".U) -> "b1001".U(4.W), - (enq === "b10110".U) -> "b1010".U(4.W), - (enq === "b10111".U) -> "b1011".U(4.W), - (enq === "b11010".U) -> "b1100".U(4.W), - (enq === "b11011".U) -> "b1101".U(4.W), - (enq === "b11100".U) -> "b1110".U(4.W), - (enq === "b11101".U) -> "b1111".U(4.W), - )) - } -} - -object Dualb4b5Encoder{ - def apply( enq: UInt ): UInt = { - require( enq.getWidth == 8, "Require Failed @ Dualb4b5Encoder!" ) - Cat( b4b5Encoder(enq(7,4)), b4b5Encoder(enq(3,0)) ) - } -} - -object Dualb4b5Decoder{ - def apply( enq: UInt ): UInt = { - require( enq.getWidth == 10, "Require Failed @ Dualb4b5Decoder!" ) - Cat( b4b5Decoder(enq(9,5)), b4b5Decoder(enq(4,0)) ) - } -} - - -class b4b5DualEncode extends Module with RequireAsyncReset{ - val io = IO(new Encode_Bundle) - - io.dataOut := Dualb4b5Encoder(io.dataIn) -} - -class b4b5DualDecode extends Module with RequireAsyncReset{ - val io = IO(new Decode_Bundle) - - io.dataOut := Dualb4b5Decoder(io.dataIn) -} +package BACK + +import chisel3._ +import chisel3.util._ + + +object b4b5Encoder{ + def apply( enq: UInt ): UInt = { + Mux1H(Seq( + (enq === "b0000".U) -> "b11110".U(5.W), + (enq === "b0001".U) -> "b01001".U(5.W), + (enq === "b0010".U) -> "b10100".U(5.W), + (enq === "b0011".U) -> "b10101".U(5.W), + (enq === "b0100".U) -> "b01010".U(5.W), + (enq === "b0101".U) -> "b01011".U(5.W), + (enq === "b0110".U) -> "b01110".U(5.W), + (enq === "b0111".U) -> "b01111".U(5.W), + (enq === "b1000".U) -> "b10010".U(5.W), + (enq === "b1001".U) -> "b10011".U(5.W), + (enq === "b1010".U) -> "b10110".U(5.W), + (enq === "b1011".U) -> "b10111".U(5.W), + (enq === "b1100".U) -> "b11010".U(5.W), + (enq === "b1101".U) -> "b11011".U(5.W), + (enq === "b1110".U) -> "b11100".U(5.W), + (enq === "b1111".U) -> "b11101".U(5.W), + )) + } +} + +object b4b5Decoder{ + def apply( enq: UInt ): UInt = { + Mux1H(Seq( + (enq === "b11110".U) -> "b0000".U(4.W), + (enq === "b01001".U) -> "b0001".U(4.W), + (enq === "b10100".U) -> "b0010".U(4.W), + (enq === "b10101".U) -> "b0011".U(4.W), + (enq === "b01010".U) -> "b0100".U(4.W), + (enq === "b01011".U) -> "b0101".U(4.W), + (enq === "b01110".U) -> "b0110".U(4.W), + (enq === "b01111".U) -> "b0111".U(4.W), + (enq === "b10010".U) -> "b1000".U(4.W), + (enq === "b10011".U) -> "b1001".U(4.W), + (enq === "b10110".U) -> "b1010".U(4.W), + (enq === "b10111".U) -> "b1011".U(4.W), + (enq === "b11010".U) -> "b1100".U(4.W), + (enq === "b11011".U) -> "b1101".U(4.W), + (enq === "b11100".U) -> "b1110".U(4.W), + (enq === "b11101".U) -> "b1111".U(4.W), + )) + } +} + +object Dualb4b5Encoder{ + def apply( enq: UInt ): UInt = { + require( enq.getWidth == 8, "Require Failed @ Dualb4b5Encoder!" ) + Cat( b4b5Encoder(enq(7,4)), b4b5Encoder(enq(3,0)) ) + } +} + +object Dualb4b5Decoder{ + def apply( enq: UInt ): UInt = { + require( enq.getWidth == 10, "Require Failed @ Dualb4b5Decoder!" ) + Cat( b4b5Decoder(enq(9,5)), b4b5Decoder(enq(4,0)) ) + } +} + + +class b4b5DualEncode extends Module with RequireAsyncReset{ + val io = IO(new Encode_Bundle) + + io.dataOut := Dualb4b5Encoder(io.dataIn) +} + +class b4b5DualDecode extends Module with RequireAsyncReset{ + val io = IO(new Decode_Bundle) + + io.dataOut := Dualb4b5Decoder(io.dataIn) +}