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滤波器触发bug修复，还是有问题

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This commit is contained in:
RuigeLee
2024-04-14 16:50:30 +08:00
parent 5da8cd77cf
commit d810ca68e6
2 changed files with 5 additions and 5 deletions
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4
src/main/scala/backBoard/BackBoardSlv.scala
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@@ -38,8 +38,8 @@ abstract class BackBoardSlvBase extends Module{
lvdsSlv.io.lvds_up_din := io.lvds_up_din
io.lvds_up_dout := lvdsSlv.io.lvds_up_dout
val downRegTemp = RegInit(VecInit(Seq.fill(32){0.U(8.W)}))
val downReg = RegInit(VecInit(Seq.fill(32){0.U(8.W)}))
val downRegTemp = RegInit(VecInit( Seq(15.U(8.W)) ++ Seq.fill(31){0.U(8.W)} ))
val downReg = RegInit(VecInit( Seq(15.U(8.W)) ++ Seq.fill(31){0.U(8.W)} ))
val upReg = WireDefault(VecInit((0 until 32).map{i => 0.U(8.W)}))
}

6
src/main/scala/backBoard/LocalRegisters.scala
View File

@@ -126,7 +126,7 @@ trait BackBoardSlvIn { this: BackBoardSlvLocal =>
def gp: Int
val flitNum = 64
val flitNum = 32
require(flitNum <= 128)
val in = IO(Input(UInt((8*gp).W)))
@@ -134,7 +134,7 @@ trait BackBoardSlvIn { this: BackBoardSlvLocal =>
val flitCnt = RegInit(MixedVecInit(Seq( 0.U(1.W), 0.U((log2Ceil(256/flitNum)).W), 0.U(1.W), 0.U(1.W), 0.U(1.W), 0.U(1.W), 0.U(1.W), 0.U(1.W), 0.U(1.W)) ))
val flitTrigger = Wire(Vec(9, Bool()))
flitTrigger(0) := true.B
flitTrigger(0) := ~RegNext(flitTrigger(0))
// flitTrigger(1) := usTrigger
@@ -202,7 +202,7 @@ trait BackBoardSlvIn { this: BackBoardSlvLocal =>
( 0 until 9 ).map{ k =>
when( digitalFilter === k.U ){
when( flitTrigger(k) ){
when( (if( k == 0 ){ true.B } else {~RegNext(flitTrigger(k)) & flitTrigger(k)}) ){
flitter(0) := in(i+8*j)
(1 until flitNum).map{ k =>
flitter(k) := flitter(k-1)