diff --git a/src/main/scala/backBoard/BackBoardSlv.scala b/src/main/scala/backBoard/BackBoardSlv.scala
index a8acac6..43ce0f6 100644
--- a/src/main/scala/backBoard/BackBoardSlv.scala
+++ b/src/main/scala/backBoard/BackBoardSlv.scala
@@ -38,8 +38,8 @@ abstract class BackBoardSlvBase extends Module{
   lvdsSlv.io.lvds_up_din    := io.lvds_up_din   
   io.lvds_up_dout   := lvdsSlv.io.lvds_up_dout
 
-  val downRegTemp = RegInit(VecInit(Seq.fill(32){0.U(8.W)}))
-  val downReg     = RegInit(VecInit(Seq.fill(32){0.U(8.W)}))
+  val downRegTemp = RegInit(VecInit( Seq(15.U(8.W)) ++ Seq.fill(31){0.U(8.W)} ))
+  val downReg     = RegInit(VecInit( Seq(15.U(8.W)) ++ Seq.fill(31){0.U(8.W)} ))
   val upReg       = WireDefault(VecInit((0 until 32).map{i => 0.U(8.W)}))
 }
 
diff --git a/src/main/scala/backBoard/LocalRegisters.scala b/src/main/scala/backBoard/LocalRegisters.scala
index 8cc402f..ca98ed9 100644
--- a/src/main/scala/backBoard/LocalRegisters.scala
+++ b/src/main/scala/backBoard/LocalRegisters.scala
@@ -126,7 +126,7 @@ trait BackBoardSlvIn { this: BackBoardSlvLocal =>
 
   def gp: Int
 
-  val flitNum = 64
+  val flitNum = 32
   require(flitNum <= 128)
 
   val in = IO(Input(UInt((8*gp).W)))
@@ -134,7 +134,7 @@ trait BackBoardSlvIn { this: BackBoardSlvLocal =>
   val flitCnt = RegInit(MixedVecInit(Seq( 0.U(1.W), 0.U((log2Ceil(256/flitNum)).W), 0.U(1.W), 0.U(1.W), 0.U(1.W), 0.U(1.W), 0.U(1.W), 0.U(1.W), 0.U(1.W)) ))
   val flitTrigger = Wire(Vec(9, Bool()))
 
-  flitTrigger(0) := true.B
+  flitTrigger(0) := ~RegNext(flitTrigger(0))
 
   // flitTrigger(1) := usTrigger
 
@@ -202,7 +202,7 @@ trait BackBoardSlvIn { this: BackBoardSlvLocal =>
 
       ( 0 until 9 ).map{ k => 
         when( digitalFilter === k.U ){
-          when( flitTrigger(k) ){
+          when( (if( k == 0 ){ true.B } else {~RegNext(flitTrigger(k)) & flitTrigger(k)}) ){
             flitter(0) := in(i+8*j)
             (1 until flitNum).map{ k =>
               flitter(k) := flitter(k-1)