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转发fifo改名

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This commit is contained in:
RuigeLee
2024-10-22 17:12:35 +08:00
parent f9d796b067
commit d7ed382897
1 changed files with 24 additions and 24 deletions
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48
src/main/scala/backBoard/shin/ShinSlv.scala
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@@ -55,8 +55,8 @@ abstract class ShinSlvPhyBase extends Module{
val maxLocalByte = OpInitByte max OpBoardCastByte max OpUniCastByte
val downStreamFifo = Module( new Queue( new AXIS_Bundle(8), 8 + headByte + 4 ) with chisel3.util.experimental.InlineInstance)
val upStreamFifo = Module( new Queue( new AXIS_Bundle(8), headByte + maxLocalByte + 4 ) with chisel3.util.experimental.InlineInstance) //4 is reserve
val downForwardFifo = Module( new Queue( new AXIS_Bundle(8), 8 + headByte + 4 ) with chisel3.util.experimental.InlineInstance)
val upForwardFifo = Module( new Queue( new AXIS_Bundle(8), headByte + maxLocalByte + 4 ) with chisel3.util.experimental.InlineInstance) //4 is reserve
val isLastDevice = Wire(Bool())
@@ -130,21 +130,21 @@ trait ShinSlvPhyDownStreamRecv{ this: ShinSlvPhyBase =>
}
//---------------
downStreamFifo.io.enq.valid :=
downForwardFifo.io.enq.valid :=
downRecvStateCurr === DownRecvStateFData & downPendBuf.io.deq.fire & ~isLastDevice
downStreamFifo.io.enq.bits.tdata := downPendBuf.io.deq.bits.tdata
downStreamFifo.io.enq.bits.tuser := downPendBuf.io.deq.bits.tuser
downStreamFifo.io.enq.bits.tlast := downRecvCnt === (downForwardDataByte) | downPendBuf.io.deq.bits.tlast
downForwardFifo.io.enq.bits.tdata := downPendBuf.io.deq.bits.tdata
downForwardFifo.io.enq.bits.tuser := downPendBuf.io.deq.bits.tuser
downForwardFifo.io.enq.bits.tlast := downRecvCnt === (downForwardDataByte) | downPendBuf.io.deq.bits.tlast
downPendBuf.io.deq.ready :=
(downRecvStateCurr === DownRecvStateOHead) |
(downRecvStateCurr === DownRecvStateSData) |
((downRecvStateCurr === DownRecvStateFData) & downStreamFifo.io.enq.ready) |
((downRecvStateCurr === DownRecvStateFData) & downForwardFifo.io.enq.ready) |
(downRecvStateCurr === DownRecvStateCRC )
when( downRecvStateCurr === DownRecvStateIdle & downRecvStateNext === DownRecvStateOHead){
isDownStreamError := false.B
} .elsewhen( downStreamFifo.io.enq.fire & downStreamFifo.io.enq.bits.tuser ){
} .elsewhen( downForwardFifo.io.enq.fire & downForwardFifo.io.enq.bits.tuser ){
isDownStreamError := true.B
printf("Warning, Wrong Package Received in DownStream, That could not happened!\n")
} .elsewhen( downRecvStateCurr === DownRecvStateOHead & downRecvStateNext === DownRecvStateIdle ){
@@ -168,7 +168,7 @@ trait ShinSlvPhyDownStreamRecv{ this: ShinSlvPhyBase =>
assert( ~(downRecvStateCurr === DownRecvStateFData & ~downStreamFifo.io.enq.ready), "Assert Failed, downStream Forward Fifo is OverFlow!" )
assert( ~(downRecvStateCurr === DownRecvStateFData & ~downForwardFifo.io.enq.ready), "Assert Failed, downStream Forward Fifo is OverFlow!" )
@@ -209,17 +209,17 @@ trait ShinSlvPhyDownStreamSend{ this: ShinSlvPhyBase =>
downStreamCdrOut.io.axis.bits.tdata := Mux1H(Seq(
( downSendStateCurr === DownSendStateNHead ) -> (downNewHead.asUInt << (downSendCnt << 3)).apply(63,56),
( downSendStateCurr === DownSendStateFData ) -> downStreamFifo.io.deq.bits.tdata,
( downSendStateCurr === DownSendStateFData ) -> downForwardFifo.io.deq.bits.tdata,
))
downStreamCdrOut.io.axis.bits.tlast := ( downSendStateCurr === DownSendStateFData ) & downStreamFifo.io.deq.bits.tlast
downStreamCdrOut.io.axis.bits.tlast := ( downSendStateCurr === DownSendStateFData ) & downForwardFifo.io.deq.bits.tlast
downStreamCdrOut.io.axis.bits.tuser :=
(( downSendStateCurr === DownSendStateFData ) & downStreamFifo.io.deq.bits.tuser ) |
(( downSendStateCurr === DownSendStateFData ) & downForwardFifo.io.deq.bits.tuser ) |
isDownStreamError
downStreamFifo.io.deq.ready :=
downForwardFifo.io.deq.ready :=
downSendStateCurr === DownSendStateFData & downStreamCdrOut.io.axis.ready
assert( ~(downStreamCdrIn.io.axis.valid & ~downStreamCdrIn.io.axis.ready) )
@@ -310,16 +310,16 @@ trait ShinSlvPhyUpStreamRecv{ this: ShinSlvPhyDownStream =>
//---------------
upStreamFifo.io.enq.valid :=
upForwardFifo.io.enq.valid :=
upRecvStateCurr === UpRecvStateFData & upPendBuf.io.deq.fire
upStreamFifo.io.enq.bits.tdata := upPendBuf.io.deq.bits.tdata
upStreamFifo.io.enq.bits.tuser := upPendBuf.io.deq.bits.tuser
upStreamFifo.io.enq.bits.tlast := upRecvCnt === (upForwardDataByte -1.U) | upPendBuf.io.deq.bits.tlast
upForwardFifo.io.enq.bits.tdata := upPendBuf.io.deq.bits.tdata
upForwardFifo.io.enq.bits.tuser := upPendBuf.io.deq.bits.tuser
upForwardFifo.io.enq.bits.tlast := upRecvCnt === (upForwardDataByte -1.U) | upPendBuf.io.deq.bits.tlast
upPendBuf.io.deq.ready :=
(upRecvStateCurr === UpRecvStateOHead) |
((upRecvStateCurr === UpRecvStateFData) & upStreamFifo.io.enq.ready) |
((upRecvStateCurr === UpRecvStateFData) & upForwardFifo.io.enq.ready) |
(upRecvStateCurr === UpRecvStateCRC )
@@ -331,7 +331,7 @@ trait ShinSlvPhyUpStreamRecv{ this: ShinSlvPhyDownStream =>
when( (upRecvStateCurr === UpRecvStateIdle & upRecvStateNext === UpRecvStateOHead) | isLastDownStreamEnd ){
isUpStreamError := false.B
} .elsewhen( upStreamFifo.io.enq.fire & upStreamFifo.io.enq.bits.tuser ){
} .elsewhen( upForwardFifo.io.enq.fire & upForwardFifo.io.enq.bits.tuser ){
isUpStreamError := true.B
printf("Warning, Wrong Package Received in UpStream, That could not happened!\n")
} .elsewhen( upRecvStateCurr === UpRecvStateOHead & upRecvStateNext === UpRecvStateIdle ){
@@ -347,7 +347,7 @@ trait ShinSlvPhyUpStreamRecv{ this: ShinSlvPhyDownStream =>
assert( ~(upRecvStateCurr === UpRecvStateFData & ~upStreamFifo.io.enq.ready), "Assert Failed, upStream Forward Fifo is OverFlow!" )
assert( ~(upRecvStateCurr === UpRecvStateFData & ~upForwardFifo.io.enq.ready), "Assert Failed, upStream Forward Fifo is OverFlow!" )
}
@@ -396,16 +396,16 @@ trait ShinSlvPhyUpStreamSend{ this: ShinSlvPhyDownStream =>
upStreamCdrOut.io.axis.bits.tdata := Mux1H(Seq(
( upSendStateCurr === UpSendStateNHead ) -> (upNewHead.asUInt << (upSendCnt << 3)).apply(63,56),
( upSendStateCurr === UpSendStateLData ) -> upReg(upSendCnt),
( upSendStateCurr === UpSendStateFData ) -> upStreamFifo.io.deq.bits.tdata,
( upSendStateCurr === UpSendStateFData ) -> upForwardFifo.io.deq.bits.tdata,
))
upStreamCdrOut.io.axis.bits.tlast := ( upSendStateCurr === UpSendStateFData ) & upStreamFifo.io.deq.bits.tlast
upStreamCdrOut.io.axis.bits.tlast := ( upSendStateCurr === UpSendStateFData ) & upForwardFifo.io.deq.bits.tlast
upStreamCdrOut.io.axis.bits.tuser :=
(( upSendStateCurr === UpSendStateFData ) & upStreamFifo.io.deq.bits.tuser ) |
(( upSendStateCurr === UpSendStateFData ) & upForwardFifo.io.deq.bits.tuser ) |
isUpStreamError
upStreamFifo.io.deq.ready :=
upForwardFifo.io.deq.ready :=
upSendStateCurr === UpSendStateFData & upStreamCdrOut.io.axis.ready
assert( ~(upStreamCdrIn.io.axis.valid & ~upStreamCdrIn.io.axis.ready) )