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框架开始收尾，协调流水线

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This commit is contained in:
Ruige Lee
2025-04-08 17:29:45 +08:00
parent e34338753a
commit d7b04710ae
3 changed files with 226 additions and 119 deletions
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57
src/main/scala/backBoard/shin/SlaveRecParser.scala
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@@ -12,21 +12,11 @@ class SlaveRecParserIO extends Module{
val stateNext = Output(UInt(4.W))
val stateCurr = Output(UInt(4.W))
val frameReq = Valid( new Bundle{
val frameLenAim = Output(UInt(12.W)) //帧长度目标
val frameStyle = Output(UInt(2.W)) //包类型
} )
val subMsgReq = Valid( new Bundle{
val subMsg_devIndex = Output(UInt(14.W)) // 子报文中设备索引
val subMsg_style = Output(UInt(2.W)) // 子报文类型
val subMsg_address = Output(UInt(16.W)) //子报文地址
val subMsg_operator = Output(UInt(4.W)) //子报文命令类型
val subMsg_length = Output(UInt(12.W)) //子报文负载长度
val subMsg_workCnt = Output(UInt(16.W)) //子报文工作计数
)
val frameReq = Valid( new FrameHeader )
val subMsgReq = Valid( new SubMsgHeader )
val resp = Input(Bool())
val isError = Output(Bool())
}
@@ -35,8 +25,6 @@ class SlaveRecParser extends Module{
val io: SlaveRecParserIO = IO(new SlaveRecParserIO)
val FRAME_STYLE_COMMON = 0.U
val FRAME_STYLE_PROBE = 1.U
@@ -59,18 +47,17 @@ class SlaveRecParser extends Module{
val lengthCnt = Reg(UInt(11.W)) //动态计数器
val frameLenCnt = Reg(UInt(12.W)) //帧长度计数
val isCrcPass: Bool
val isTxEnd: Bool
val isShortRx: Bool //接收长度小于预期
val frameLenAim = Reg(UInt(12.W)); io.frameLenAim := frameLenAim //帧长度目标
val frameStyle = Reg(UInt(2.W)); io.frameStyle := frameStyle //包类型
val subMsg_devIndex = Reg(UInt(14.W)); io.subMsg_devIndex := subMsg_devIndex // 子报文中设备索引
val subMsg_style = Reg(UInt(2.W)); io.subMsg_style := subMsg_style // 子报文类型
val subMsg_address = Reg(UInt(16.W)); io.subMsg_address := subMsg_address //子报文地址
val subMsg_operator = Reg(UInt(4.W)); io.subMsg_operator := subMsg_operator //子报文命令类型
val subMsg_length = Reg(UInt(12.W)); io.subMsg_length := subMsg_length //子报文负载长度
val subMsg_workCnt = Reg(UInt(16.W)); io.subMsg_workCnt := subMsg_workCnt //子报文工作计数
val devIndex = Reg(UInt(14.W)); io.subMsgReq.devIndex := devIndex // 子报文中设备索引
val style = Reg(UInt(2.W)); io.subMsgReq.style := style // 子报文类型
val address = Reg(UInt(16.W)); io.subMsgReq.address := address //子报文地址
val operator = Reg(UInt(4.W)); io.subMsgReq.operator := operator //子报文命令类型
val length = Reg(UInt(12.W)); io.subMsgReq.length := length //子报文负载长度
val workCnt = Reg(UInt(16.W)); io.subMsgReq.workCnt := workCnt //子报文工作计数
when( stateCurr === STATE_HEADER & lengthCnt === 0.U ){
@@ -81,29 +68,29 @@ class SlaveRecParser extends Module{
}
when( stateCurr === STATE_PAYLOAD_INDEX_STYLE & lengthCnt === 0.U ){
subMsg_devIndex := io.rec.bits.tdata << 6
devIndex := io.rec.bits.tdata << 6
} .elsewhen( stateCurr === STATE_PAYLOAD_INDEX_STYLE & lengthCnt === 1.U ){
subMsg_devIndex := subMsg_devIndex | io.rec.bits.tdata(7,2)
subMsg_style := io.rec.bits.tdata(1,0)
devIndex := devIndex | io.rec.bits.tdata(7,2)
style := io.rec.bits.tdata(1,0)
}
when( stateCurr === STATE_PAYLOAD_ADDR & lengthCnt === 0.U ){
subMsg_address := io.rec.bits.tdata << 8
address := io.rec.bits.tdata << 8
} .elsewhen( stateCurr === STATE_PAYLOAD_ADDR & lengthCnt === 1.U ){
subMsg_address := subMsg_address | io.rec.bits.tdata
address := address | io.rec.bits.tdata
}
when( stateCurr === STATE_PAYLOAD_OP_LENGTH & lengthCnt === 0.U ){
subMsg_operator := io.rec.bits.tdata(7,4)
subMsg_length := io.rec.bits.tdata(3,0) << 8
operator := io.rec.bits.tdata(7,4)
length := io.rec.bits.tdata(3,0) << 8
} .elsewhen( stateCurr === STATE_PAYLOAD_OP_LENGTH & lengthCnt === 1.U ){
subMsg_length := subMsg_length | io.rec.bits.tdata(7,0)
length := length | io.rec.bits.tdata(7,0)
}
when( stateCurr === STATE_PAYLOAD_WORKCNT & lengthCnt === 0.U ){
subMsg_workCnt := io.rec.bits.tdata(7,0) << 8
workCnt := io.rec.bits.tdata(7,0) << 8
} .elsewhen( stateCurr === STATE_PAYLOAD_WORKCNT & lengthCnt === 1.U ){
subMsg_workCnt := subMsg_workCnt | io.rec.bits.tdata(7,0)
workCnt := workCnt | io.rec.bits.tdata(7,0)
}
@@ -139,8 +126,8 @@ class SlaveRecParser extends Module{
( stateCurr === STATE_CRC ) -> Mux( isShortRx, STATE_ERROR,
Mux( lengthCnt === (4 - 1).U, Mux( isCrcPass, STATE_IDLE, STATE_ERROR), STATE_CRC )
),
( stateCurr === STATE_ERROR ) -> Mux( isTxEnd, STATE_IDLE, STATE_ERROR ),
( stateCurr === STATE_WAIT ) ->
( stateCurr === STATE_ERROR ) -> Mux( io.resp, STATE_IDLE, STATE_ERROR ),
( stateCurr === STATE_WAIT ) -> Mux( io.resp, STATE_IDLE, STATE_ERROR )
))