框架开始收尾，协调流水线
This commit is contained in:
Ruige Lee
@@ -10,12 +10,12 @@ class FrameHeader extends Bundle{
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}
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class SubMsgHeader extends Bundle{
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val subMsg_devIndex = UInt(14.W) // 子报文中设备索引
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val subMsg_style = UInt(2.W) // 子报文类型
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val subMsg_address = UInt(16.W) //子报文地址
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val subMsg_operator = UInt(4.W) //子报文命令类型
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val subMsg_length = UInt(12.W) //子报文负载长度
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val subMsg_workCnt = UInt(16.W) //子报文工作计数
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val devIndex = UInt(14.W) // 子报文中设备索引
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val style = UInt(2.W) // 子报文类型
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val address = UInt(16.W) //子报文地址
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val operator = UInt(4.W) //子报文命令类型
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val length = UInt(12.W) //子报文负载长度
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val workCnt = UInt(16.W) //子报文工作计数
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}
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@@ -56,8 +56,7 @@ abstract class SlaveParserBase extends Module{
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val upSendGen = Module(new SlaveSendGen)
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val downRecFifo = for( i <- 0 until 2 ) yield { Module(new Queue(UInt(8.W), 8)) }
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val upRecFifo = for( i <- 0 until 2 ) yield { Module(new Queue(UInt(8.W), 8)) }
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val downSinkSel = Reg(Bool())
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@@ -76,6 +75,9 @@ abstract class SlaveParserBase extends Module{
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val isUpSendPend = RegInit(false.B)
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//处理主报文
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//同时到来怎么办
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when( downRecParser.io.frameReq.fire ){
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when(downRecParser.io.frameReq.bits.frameStyle === FRAME_STYLE_PROBE){ //下行来了一个嗅探包
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@@ -118,13 +120,14 @@ abstract class SlaveParserBase extends Module{
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}
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upSendGen.io.frameReq.valid :=
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isUpSendPend | isUpSendProbe //上行转发 | 上行探针
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isUpSendPend | isUpSendProbe | //上行转发 | 上行探针 | 下行回环
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assert( OneHot(isUpSendPend, isUpSendProbe) )
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upSendGen.io.frameReq.bits := Mux1H(Seq(
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isUpSendPend -> upFrameInfo, //上行转发
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isUpSendProbe -> probeFrame, //上行探针
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, //下行回环
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))
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@@ -139,91 +142,217 @@ abstract class SlaveParserBase extends Module{
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//子报文
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val isDownSubMsgValid = for( i <- 0 until 2 ) yield { RegInit(false.B) }
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val isUpSubMsgValid = for( i <- 0 until 2 ) yield { RegInit(false.B) }
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//接收子报文
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upSendFifo.io.enq.bits := Mux1H(Seq(
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( downRecParser.io.frameStyle === FRAME_STYLE_PROBE & downRecParser.io.stateCurr > STATE_HEADER ) -> downRecParser.io.data.bits //嗅探包 bypass到上行
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val downSubMsgInfo = for( i <- 0 until 2 ) yield { Reg(new SubMsgHeader) }
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val upSubMsgInfo = for( i <- 0 until 2 ) yield { Reg(new SubMsgHeader) }
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val downRecFifo = for( i <- 0 until 2 ) yield { Module(new Queue(UInt(8.W), 8)) }
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val upRecFifo = for( i <- 0 until 2 ) yield { Module(new Queue(UInt(8.W), 8)) }
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val isDownRecPing: Bool
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val isUpRecPing: Bool
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//下行接收
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when( downRecParser.io.subMsgReq.fire ){
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when( isDownRecPing ){
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isDownSubMsgValid(0) := true.B
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downSubMsgInfo(0).devIndex := downRecParser.io.subMsgReq.bits.devIndex
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downSubMsgInfo(0).style := downRecParser.io.subMsgReq.bits.style
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downSubMsgInfo(0).address := downRecParser.io.subMsgReq.bits.address
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downSubMsgInfo(0).operator := downRecParser.io.subMsgReq.bits.operator
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downSubMsgInfo(0).length := downRecParser.io.subMsgReq.bits.length
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downSubMsgInfo(0).workCnt := downRecParser.io.subMsgReq.bits.workCnt
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downSubMsgInfo(0).source := 0.U
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//override 自身包
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when( downRecParser.io.subMsgReq.bits.devIndex === localDevIndex ){
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when( downRecParser.io.subMsgReq.bits.operator === 1.U ) {//写 sparser -》sram
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downSubMsgInfo(0).workCnt := downRecParser.io.subMsgReq.bits.workCnt + 1.U
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} .elsewhen( downRecParser.io.subMsgReq.bits.operator === 2.U ) {//读 ram ->fifo
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} .elsewhen( downRecParser.io.subMsgReq.bits.operator === 3.U ) {//读写 parser -》sram sram ->fifo
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downSubMsgInfo(0).workCnt := downRecParser.io.subMsgReq.bits.workCnt + 1.U
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}
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}
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} .otherwise{
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isDownSubMsgValid(1) := true.B
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downSubMsgInfo(1).devIndex := downRecParser.io.subMsgReq.bits.devIndex
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downSubMsgInfo(1).style := downRecParser.io.subMsgReq.bits.style
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downSubMsgInfo(1).address := downRecParser.io.subMsgReq.bits.address
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downSubMsgInfo(1).operator := downRecParser.io.subMsgReq.bits.operator
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downSubMsgInfo(1).length := downRecParser.io.subMsgReq.bits.length
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downSubMsgInfo(1).workCnt := downRecParser.io.subMsgReq.bits.workCnt
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downSubMsgInfo(1).source := 1.U
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//override 自身包
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when( downRecParser.io.subMsgReq.bits.devIndex === localDevIndex ){
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when( downRecParser.io.subMsgReq.bits.operator === 1.U ) {//写 sparser -》sram
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downSubMsgInfo(1).workCnt := downRecParser.io.subMsgReq.bits.workCnt + 1.U
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} .elsewhen( downRecParser.io.subMsgReq.bits.operator === 2.U ) {//读 ram ->fifo
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} .elsewhen( downRecParser.io.subMsgReq.bits.operator === 3.U ) {//读写 parser -》sram sram ->fifo
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downSubMsgInfo(1).workCnt := downRecParser.io.subMsgReq.bits.workCnt + 1.U
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}
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}
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}
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}
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when( isDownRecPing ){
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downRecFifo(0).io.enq.valid := downRecParser.io.data.valid
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downRecFifo(0).io.enq.bits := downRecParser.io.data.bits
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downRecParser.io.data.ready := downRecFifo(0).io.enq.ready
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} .otherwise{
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downRecFifo(1).io.enq.valid := downRecParser.io.data.valid
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downRecFifo(1).io.enq.bits := downRecParser.io.data.bits
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downRecParser.io.data.ready := downRecFifo(1).io.enq.ready
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}
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//写入sram
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sram.io.enw :=
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( isDownRecPing & downSubMsgInfo(0).devIndex === localDevIndex & (downSubMsgInfo(0).operator === 1.U | downSubMsgInfo(0).operator === 3.U)) |
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(~isDownRecPing & downSubMsgInfo(1).devIndex === localDevIndex & (downSubMsgInfo(1).operator === 1.U | downSubMsgInfo(1).operator === 3.U))
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))
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upSendFifo.io.enq.valid :=
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((downRecParser.io.frameStyle === FRAME_STYLE_PROBE & downRecParser.io.stateCurr > STATE_HEADER ) & downRecParser.io.data.valid) |
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downRecParser.io.data.ready :=
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((downRecParser.io.frameStyle === FRAME_STYLE_PROBE & downRecParser.io.stateCurr > STATE_HEADER ) & upSendFifo.io.enq.ready ) |
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downSendFifo.io.enq.bits := Mux1H(Seq(
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( downRecParser.io.frameStyle === FRAME_STYLE_COMMON & downRecParser.io.stateCurr > STATE_HEADER ) ->
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))
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val isDownIdle
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val isDownBypassToDown
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val isDownWriteToSRAM
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val isDownReadFromSRAM
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val isDownLoopBack
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val isUpIdle
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val isUpBypassToUp
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val isUpWriteToSRAM
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val isUpReadFromSRAM
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val isUpBlackHole
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sram.io.addrw :=
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sram.io.dataw := downRecParser.io.data.bits
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//上行接收
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when( upRecParser.io.subMsgReq.fire ){
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when( isUpRecFifoPing ){
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isUpSubMsgValid(0) := true.B
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// val downOutFifo = Module(new Queue(UInt(8.W), 8))
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val upInFifo = Module(new Queue(UInt(8.W), 8))
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// val upOutFifo = Module(new Queue(UInt(8.W), 8))
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upSubMsgInfo(0).devIndex := upRecParser.io.subMsgReq.bits.devIndex
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upSubMsgInfo(0).style := upRecParser.io.subMsgReq.bits.style
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upSubMsgInfo(0).address := upRecParser.io.subMsgReq.bits.address
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upSubMsgInfo(0).operator := upRecParser.io.subMsgReq.bits.operator
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upSubMsgInfo(0).length := upRecParser.io.subMsgReq.bits.length
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upSubMsgInfo(0).workCnt := upRecParser.io.subMsgReq.bits.workCnt
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upSubMsgInfo(0).source := 0.U
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//override 自身包
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when( upRecParser.io.subMsgReq.bits.devIndex === localDevIndex ){
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when( upRecParser.io.subMsgReq.bits.operator === 1.U ) {//写 sparser -》sram
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} .elsewhen( upRecParser.io.subMsgReq.bits.operator === 2.U ) {//读 ram ->fifo
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upSubMsgInfo(0).workCnt := upRecParser.io.subMsgReq.bits.workCnt + 1.U
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} .elsewhen( upRecParser.io.subMsgReq.bits.operator === 3.U ) {//读写 parser -》sram sram ->fifo
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upSubMsgInfo(0).workCnt := upRecParser.io.subMsgReq.bits.workCnt + 1.U
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}
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}
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} .otherwise{
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isUpSubMsgValid(1) := true.B
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upSubMsgInfo(1).devIndex := upRecParser.io.subMsgReq.bits.devIndex
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upSubMsgInfo(1).style := upRecParser.io.subMsgReq.bits.style
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upSubMsgInfo(1).address := upRecParser.io.subMsgReq.bits.address
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upSubMsgInfo(1).operator := upRecParser.io.subMsgReq.bits.operator
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upSubMsgInfo(1).length := upRecParser.io.subMsgReq.bits.length
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upSubMsgInfo(1).workCnt := upRecParser.io.subMsgReq.bits.workCnt
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upSubMsgInfo(1).source := 1.U
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//override 自身包
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when( upRecParser.io.subMsgReq.bits.devIndex === localDevIndex ){
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when( upRecParser.io.subMsgReq.bits.operator === 1.U ) {//写 sparser -》sram
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} .elsewhen( upRecParser.io.subMsgReq.bits.operator === 2.U ) {//读 ram ->fifo
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upSubMsgInfo(1).workCnt := upRecParser.io.subMsgReq.bits.workCnt + 1.U
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} .elsewhen( upRecParser.io.subMsgReq.bits.operator === 3.U ) {//读写 parser -》sram sram ->fifo
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upSubMsgInfo(1).workCnt := upRecParser.io.subMsgReq.bits.workCnt + 1.U
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}
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}
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}
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}
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when( isUpRecFifoPing ){
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upRecFifo(0).io.enq.valid := upRecParser.io.data.valid
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upRecFifo(0).io.enq.bits :=
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Mux( upSubMsgInfo(0).devIndex === localDevIndex & (upSubMsgInfo(0).operator === 2.U | upSubMsgInfo(0).operator === 3.U),
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sram.io.datar, upRecParser.io.data.bits)
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downInFifo.io.enq <> io.downIn
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upRecParser.io.data.ready := upRecFifo(0).io.enq.ready
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} .otherwise{
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upRecFifo(1).io.enq.valid := upRecParser.io.data.valid
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upRecFifo(1).io.enq.bits := Mux( upSubMsgInfo(1).devIndex === localDevIndex & (upSubMsgInfo(1).operator === 2.U | upSubMsgInfo(1).operator === 3.U),
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sram.io.datar, upRecParser.io.data.bits)
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upRecParser.io.data.ready := upRecFifo(1).io.enq.ready
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}
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io.downOut.valid :=
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( === FRAME_STYLE_COMMON ) &
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io.upOut.valid :=
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( === FRAME_STYLE_PROBE) & |
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io.upOut.bits :=
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Mux1H(Seq(
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( === FRAME_STYLE_PROBE) -> downInFifo.io.deq.bits, //嗅探包情形
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-> upInFifo.io.deq.bits, //上行
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-> //上行修正数据
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))
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io.downOut.bits :=
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Mux1H(Seq(
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-> //自主发送嗅探包
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( ) -> downInFifo.io.deq.bits, //下行
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( ) -> //下行修正数据
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))
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downInFifo.io.deq.ready :=
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upInFifo.io.deq.ready :=
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//读出SRAM
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sram.io.enr :=
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( isUpRecFifoPing & upSubMsgInfo(0).devIndex === localDevIndex & (upSubMsgInfo(0).operator === 1.U | upSubMsgInfo(0).operator === 3.U)) |
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(~isUpRecFifoPing & upSubMsgInfo(1).devIndex === localDevIndex & (upSubMsgInfo(1).operator === 1.U | upSubMsgInfo(1).operator === 3.U))
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sram.io.addrr :=
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//子报文下行发送
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val isDownSendPing: Bool
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val isUpSendPing: Bool
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val isLastDevice: Bool
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downSendGen.io.subMsgReq.valid :=
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( isDownSendPing & isDownSubMsgValid(0) ) | (~isDownSendPing & isDownSubMsgValid(1))
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downSendGen.io.subMsgReq.bits := Mux( isDownSendPing, downSubMsgInfo(0), downSubMsgInfo(1) )
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when( downSendGen.io.subMsgReq.fire ){ //ready
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isDownSendPing := ~isDownSendPing
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when( isDownSendPing ){
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isDownSubMsgValid(0) := false.B
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} .otherwise{
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isDownSubMsgValid(1) := false.B
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}
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}
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downRecFifo(0).io.deq <> downSendGen.io.data(0)
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downRecFifo(1).io.deq <> downSendGen.io.data(1)
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//子报文上行发送
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upSendGen.io.subMsgReq.valid :=
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( isUpSendPing & isUpSubMsgValid(0) ) | (~isUpSendPing & isUpSubMsgValid(1))
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upSendGen.io.subMsgReq.bits := Mux( isUpSendPing, upSubMsgInfo(0), upSubMsgInfo(1) )
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when( upSendGen.io.subMsgReq.fire ){ //ready
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isUpSendPing := ~isUpSendPing
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when( isUpSendPing ){
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isUpSubMsgValid(0) := false.B
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} .otherwise{
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isUpSubMsgValid(1) := false.B
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}
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}
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upRecFifo(0).io.deq <> upSendGen.io.data(0)
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upRecFifo(1).io.deq <> upSendGen.io.data(1)
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when(isLastDevice & downRecParser.io.stateCurr > ){
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downSendGen.io.send <> upRecParser.io.rec
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}
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Block a user