允许修改从机寄存器访问个数

src/main/scala/backBoard/BackBoardSlv.scala

@@ -47,15 +47,14 @@ abstract class BackBoardSlvBase extends Module{
 trait BackBoardSlvDown{ this: BackBoardSlvBase =>
 
 
-  val downCnt = RegInit(0.U(6.W))
-  val downTimeoutEn  = RegInit( false.B )
-  val downTimeoutRst = (downCnt === 0.U & lvdsSlv.io.downstream_rx_data_valid)
-  val ( _, downTimeout ) = Counter( Range( 0,1000 ), downTimeoutEn, downTimeoutRst )
-
+  val downCnt = Reg(UInt(6.W))
 
 
   when( lvdsSlv.io.downstream_rx_data_valid ){
     downRegTemp(downCnt) := lvdsSlv.io.downstream_rx_data_out
+    downCnt := downCnt + 1.U
+  } .otherwise{
+    downCnt := 0.U
   }
 
   when( lvdsSlv.io.downstream_rx_crc_valid ){
@@ -64,56 +63,23 @@ trait BackBoardSlvDown{ this: BackBoardSlvBase =>
     }
   }
 
-
-  when( downTimeout ){
-    downTimeoutEn := false.B
-  } .elsewhen( downCnt === 32.U ){
-    downTimeoutEn := false.B
-  } .elsewhen(downCnt === 0.U & lvdsSlv.io.downstream_rx_data_valid){
-    downTimeoutEn := true.B
-  }
-
-  when( downTimeout ){
-    downCnt := 0.U
-  }.elsewhen( downCnt === 32.U ){
-    downCnt := 0.U
-  }.elsewhen( lvdsSlv.io.downstream_rx_data_valid ){
-    downCnt := downCnt + 1.U
-  }
-
-
 }
 
 trait BackBoardSlvUp{ this: BackBoardSlvBase =>
 
-  val upCnt = RegInit(31.U(6.W))
-  val upTimeoutEn  = RegInit( false.B )
-  val upTimeoutRst = (upCnt === 0.U & lvdsSlv.io.upstream_tx_data_ready)
-  val ( _, upTimeout ) = Counter( Range( 0,1000 ), upTimeoutEn, upTimeoutRst )
-
+  val upCnt = Reg(UInt(6.W))
 
   lvdsSlv.io.upstream_tx_data_in := upReg(upCnt)
 
-
-
-  when( upTimeout ){
-    upTimeoutEn := false.B
-  } .elsewhen( upCnt === 31.U ){
-    upTimeoutEn := false.B
-  } .elsewhen(upCnt === 0.U & lvdsSlv.io.upstream_tx_data_ready){
-    upTimeoutEn := true.B
-  }
-
-  when( upTimeout ){
-    upCnt := 0.U
-  }.elsewhen( lvdsSlv.io.upstream_tx_data_ready ){
-    when(upCnt === 31.U){
-      upCnt := 0.U        
-    } .elsewhen( lvdsSlv.io.upstream_tx_data_ready ){
+  when( lvdsSlv.io.upstream_tx_data_ready ){
+    when( ~RegNext(lvdsSlv.io.upstream_tx_data_ready, false.B) ){
+      upCnt := 0.U
+    } .otherwise{
       upCnt := upCnt + 1.U
     }
   }
 
+
 }