diff --git a/src/main/scala/backBoard/BackBoardMst.scala b/src/main/scala/backBoard/BackBoardMst.scala
index 0bbc99e..a0fb3dc 100644
--- a/src/main/scala/backBoard/BackBoardMst.scala
+++ b/src/main/scala/backBoard/BackBoardMst.scala
@@ -59,6 +59,7 @@ class BackBoardMstBase extends Module{ //10M
   val linkNum = RegInit(0.U(7.W))
   val testReg = RegInit("haa55".U(16.W))
   val interrupt = RegInit(false.B); io.interrupt := interrupt
+  val slaveDataLength    = RegInit(((8/8)*32-1).U(8.W))
 
   lvdsMst.io.rst_n       := ~reset.asBool
   lvdsMst.io.reset_calib := io.reset_calib
@@ -148,6 +149,7 @@ trait BackBoardMstFSMC{ this: BackBoardMstBase =>
       ( activeAddr === 3.U) -> slvOffLine,
       ( activeAddr === 4.U) -> testReg,
       ( activeAddr === 5.U) -> linkNum,
+      ( activeAddr === 6.U) -> slaveDataLength,
     ))
 
 
@@ -203,6 +205,10 @@ trait BackBoardMstFSMC{ this: BackBoardMstBase =>
       testReg := wrRegData
     }
 
+    when( wrRegAddr === 6.U ){
+      slaveDataLength := wrRegData
+    }
+
   }
 
 }
@@ -242,12 +248,12 @@ with BackBoardMstFSMC
 
   val frame_info_update_en = RegInit(false.B)
   val slave_type_num       = RegInit(0.U(8.W))
-  val slave_data_length    = RegInit(0.U(8.W))
+
   val tx_start             = RegInit(false.B)
 
   lvdsMst.io.frame_info_update_en := frame_info_update_en
   lvdsMst.io.slave_type_num       := slave_type_num
-  lvdsMst.io.slave_data_length    := slave_data_length
+  lvdsMst.io.slave_data_length    := slaveDataLength
   lvdsMst.io.tx_start := tx_start
 
   val stateCur = RegInit(15.U(4.W))
@@ -266,7 +272,6 @@ trait BackBoardMstLVDSInit{ this: BackBoardMstLVDSBase =>
 
       frame_info_update_en := false.B
       slave_type_num       := 0.U
-      slave_data_length    := 0.U
 
       tx_start := false.B
       
@@ -275,7 +280,7 @@ trait BackBoardMstLVDSInit{ this: BackBoardMstLVDSBase =>
 
       frame_info_update_en := true.B
       slave_type_num       := Cat( "b00".U(2.W), slvNum )
-      slave_data_length    := ((8/8)*32-1).U
+      slaveDataLength      := slaveDataLength
 
       tx_start := false.B
     } .elsewhen( stateCur === 1.U ){ // tx start
@@ -322,14 +327,13 @@ trait BackBoardMstLVDSSync{ this: BackBoardMstLVDSBase =>
       stateCur := 0.U
       frame_info_update_en := false.B
       slave_type_num       := 0.U
-      slave_data_length    := 0.U
       tx_start := false.B
     }.elsewhen( stateCur === 0.U ){
       stateCur := 1.U
 
       frame_info_update_en := true.B
       slave_type_num       := Cat( "b01".U(2.W), slvNum )
-      slave_data_length    := ((8/8)*32-1).U
+      slaveDataLength      := slaveDataLength
 
       tx_start := false.B
     } .elsewhen( stateCur === 1.U ){ // tx start
@@ -370,7 +374,6 @@ trait BackBoardMstLVDSTransmit{ this: BackBoardMstLVDSBase =>
 
       frame_info_update_en := false.B
       slave_type_num       := 0.U
-      slave_data_length    := 0.U
 
       tx_start := false.B
       
@@ -380,7 +383,7 @@ trait BackBoardMstLVDSTransmit{ this: BackBoardMstLVDSBase =>
 
       frame_info_update_en := true.B
       slave_type_num       := Cat( "b10".U(2.W), slvNum )
-      slave_data_length    := ((8/8)*32-1).U
+      slaveDataLength      := slaveDataLength
 
       tx_start := false.B
     } .elsewhen( stateCur === 1.U ){ // tx start
diff --git a/src/main/scala/backBoard/BackBoardSlv.scala b/src/main/scala/backBoard/BackBoardSlv.scala
index 31a1296..6eaad67 100644
--- a/src/main/scala/backBoard/BackBoardSlv.scala
+++ b/src/main/scala/backBoard/BackBoardSlv.scala
@@ -47,15 +47,14 @@ abstract class BackBoardSlvBase extends Module{
 trait BackBoardSlvDown{ this: BackBoardSlvBase =>
 
 
-  val downCnt = RegInit(0.U(6.W))
-  val downTimeoutEn  = RegInit( false.B )
-  val downTimeoutRst = (downCnt === 0.U & lvdsSlv.io.downstream_rx_data_valid)
-  val ( _, downTimeout ) = Counter( Range( 0,1000 ), downTimeoutEn, downTimeoutRst )
-
+  val downCnt = Reg(UInt(6.W))
 
 
   when( lvdsSlv.io.downstream_rx_data_valid ){
     downRegTemp(downCnt) := lvdsSlv.io.downstream_rx_data_out
+    downCnt := downCnt + 1.U
+  } .otherwise{
+    downCnt := 0.U
   }
 
   when( lvdsSlv.io.downstream_rx_crc_valid ){
@@ -64,56 +63,23 @@ trait BackBoardSlvDown{ this: BackBoardSlvBase =>
     }
   }
 
-
-  when( downTimeout ){
-    downTimeoutEn := false.B
-  } .elsewhen( downCnt === 32.U ){
-    downTimeoutEn := false.B
-  } .elsewhen(downCnt === 0.U & lvdsSlv.io.downstream_rx_data_valid){
-    downTimeoutEn := true.B
-  }
-
-  when( downTimeout ){
-    downCnt := 0.U
-  }.elsewhen( downCnt === 32.U ){
-    downCnt := 0.U
-  }.elsewhen( lvdsSlv.io.downstream_rx_data_valid ){
-    downCnt := downCnt + 1.U
-  }
-
-
 }
 
 trait BackBoardSlvUp{ this: BackBoardSlvBase =>
 
-  val upCnt = RegInit(31.U(6.W))
-  val upTimeoutEn  = RegInit( false.B )
-  val upTimeoutRst = (upCnt === 0.U & lvdsSlv.io.upstream_tx_data_ready)
-  val ( _, upTimeout ) = Counter( Range( 0,1000 ), upTimeoutEn, upTimeoutRst )
-
+  val upCnt = Reg(UInt(6.W))
 
   lvdsSlv.io.upstream_tx_data_in := upReg(upCnt)
 
-
-
-  when( upTimeout ){
-    upTimeoutEn := false.B
-  } .elsewhen( upCnt === 31.U ){
-    upTimeoutEn := false.B
-  } .elsewhen(upCnt === 0.U & lvdsSlv.io.upstream_tx_data_ready){
-    upTimeoutEn := true.B
-  }
-
-  when( upTimeout ){
-    upCnt := 0.U
-  }.elsewhen( lvdsSlv.io.upstream_tx_data_ready ){
-    when(upCnt === 31.U){
-      upCnt := 0.U        
-    } .elsewhen( lvdsSlv.io.upstream_tx_data_ready ){
+  when( lvdsSlv.io.upstream_tx_data_ready ){
+    when( ~RegNext(lvdsSlv.io.upstream_tx_data_ready, false.B) ){
+      upCnt := 0.U
+    } .otherwise{
       upCnt := upCnt + 1.U
     }
   }
 
+
 }