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允许修改从机寄存器访问个数

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This commit is contained in:
RuigeLee
2024-03-20 16:00:42 +08:00
parent 63ec7859a6
commit d64fa778ae
2 changed files with 21 additions and 52 deletions
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19
src/main/scala/backBoard/BackBoardMst.scala
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@@ -59,6 +59,7 @@ class BackBoardMstBase extends Module{ //10M
val linkNum = RegInit(0.U(7.W))
val testReg = RegInit("haa55".U(16.W))
val interrupt = RegInit(false.B); io.interrupt := interrupt
val slaveDataLength = RegInit(((8/8)*32-1).U(8.W))
lvdsMst.io.rst_n := ~reset.asBool
lvdsMst.io.reset_calib := io.reset_calib
@@ -148,6 +149,7 @@ trait BackBoardMstFSMC{ this: BackBoardMstBase =>
( activeAddr === 3.U) -> slvOffLine,
( activeAddr === 4.U) -> testReg,
( activeAddr === 5.U) -> linkNum,
( activeAddr === 6.U) -> slaveDataLength,
))
@@ -203,6 +205,10 @@ trait BackBoardMstFSMC{ this: BackBoardMstBase =>
testReg := wrRegData
}
when( wrRegAddr === 6.U ){
slaveDataLength := wrRegData
}
}
}
@@ -242,12 +248,12 @@ with BackBoardMstFSMC
val frame_info_update_en = RegInit(false.B)
val slave_type_num = RegInit(0.U(8.W))
val slave_data_length = RegInit(0.U(8.W))
val tx_start = RegInit(false.B)
lvdsMst.io.frame_info_update_en := frame_info_update_en
lvdsMst.io.slave_type_num := slave_type_num
lvdsMst.io.slave_data_length := slave_data_length
lvdsMst.io.slave_data_length := slaveDataLength
lvdsMst.io.tx_start := tx_start
val stateCur = RegInit(15.U(4.W))
@@ -266,7 +272,6 @@ trait BackBoardMstLVDSInit{ this: BackBoardMstLVDSBase =>
frame_info_update_en := false.B
slave_type_num := 0.U
slave_data_length := 0.U
tx_start := false.B
@@ -275,7 +280,7 @@ trait BackBoardMstLVDSInit{ this: BackBoardMstLVDSBase =>
frame_info_update_en := true.B
slave_type_num := Cat( "b00".U(2.W), slvNum )
slave_data_length := ((8/8)*32-1).U
slaveDataLength := slaveDataLength
tx_start := false.B
} .elsewhen( stateCur === 1.U ){ // tx start
@@ -322,14 +327,13 @@ trait BackBoardMstLVDSSync{ this: BackBoardMstLVDSBase =>
stateCur := 0.U
frame_info_update_en := false.B
slave_type_num := 0.U
slave_data_length := 0.U
tx_start := false.B
}.elsewhen( stateCur === 0.U ){
stateCur := 1.U
frame_info_update_en := true.B
slave_type_num := Cat( "b01".U(2.W), slvNum )
slave_data_length := ((8/8)*32-1).U
slaveDataLength := slaveDataLength
tx_start := false.B
} .elsewhen( stateCur === 1.U ){ // tx start
@@ -370,7 +374,6 @@ trait BackBoardMstLVDSTransmit{ this: BackBoardMstLVDSBase =>
frame_info_update_en := false.B
slave_type_num := 0.U
slave_data_length := 0.U
tx_start := false.B
@@ -380,7 +383,7 @@ trait BackBoardMstLVDSTransmit{ this: BackBoardMstLVDSBase =>
frame_info_update_en := true.B
slave_type_num := Cat( "b10".U(2.W), slvNum )
slave_data_length := ((8/8)*32-1).U
slaveDataLength := slaveDataLength
tx_start := false.B
} .elsewhen( stateCur === 1.U ){ // tx start