修改Makefile的模拟策略

This commit is contained in:
2025-09-22 15:43:14 +08:00
parent 8ed508f655
commit d611a1644b

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@@ -5,6 +5,12 @@ ISR_MARCH=-march=rv32i -mabi=ilp32
APP_MARCH=-march=rv32i -mabi=ilp32 APP_MARCH=-march=rv32i -mabi=ilp32
ISR_CFLAGS=-O2 ISR_CFLAGS=-O2
APP_CFLAGS=-O2 APP_CFLAGS=-O2
SPI_TYPE ?= -spi 0
TRANS_CODE ?=
DEVCLK ?= --dev1 0 90 --dev2 0 -90
CDRCLK ?= --clk 0 40
ifeq "$(RVCCVERSION)" "12.2.0" ifeq "$(RVCCVERSION)" "12.2.0"
ISR_MARCH=-march=rv32izicsr -mabi=ilp32 ISR_MARCH=-march=rv32izicsr -mabi=ilp32
APP_MARCH=-march=rv32izicsr -mabi=ilp32 APP_MARCH=-march=rv32izicsr -mabi=ilp32
@@ -12,31 +18,13 @@ endif
.PHONY: compile tb wave .PHONY: compile tb wave
shin: shin:
rm -f ./generated/shin/* rm -f ./generated/shin/*
rm -f ./generated/SimCDR/* rm -f ./generated/SimCDR/*
sbt "test:runMain test.testShinModule" sbt "test:runMain test.testShinModule"
testShin: testShin:
python3 ./tb/shinTest/gen_pkt.py python3 ./tb/shinTest/gen_pkt.py ${SPI_TYPE} ${TRANS_CODE}
mkdir -p generated/log
rm -rf generated/log/*
iverilog -Wall \
-o ./tb/build/shinTest.iverilog \
-y ./generated/shin \
-I ./generated/shin \
-D RANDOMIZE_REG_INIT \
-D IVERILOG_COMPILE \
./tb/shinTest/ShinTopSpiTb.v
vvp -N ./tb/build/shinTest.iverilog -lxt2 -fst || true
python3 ./tb/shinTest/check_testcase.py
testShin8b10b:
python3 ./tb/shinTest/gen_pkt.py -8b10b
mkdir -p generated/log mkdir -p generated/log
rm -rf generated/log/* rm -rf generated/log/*
iverilog -Wall \ iverilog -Wall \
@@ -50,7 +38,7 @@ testShin8b10b:
python3 ./tb/shinTest/check_testcase.py python3 ./tb/shinTest/check_testcase.py
testShinClk: testShinClk:
python3 ./tb/shinTest/gen_pkt_clk.py --dev1 0 92 --dev2 0 -92 -8b10b python3 ./tb/shinTest/gen_pkt_clk.py ${DEVCLK} ${SPI_TYPE} ${TRANS_CODE}
mkdir -p generated/log mkdir -p generated/log
rm -rf generated/log/* rm -rf generated/log/*
iverilog -Wall \ iverilog -Wall \
@@ -64,7 +52,7 @@ testShinClk:
python3 ./tb/shinTest/check_testcase.py python3 ./tb/shinTest/check_testcase.py
testCDR: testCDR:
python3 ./tb/shinTest/gen_sim_cdr_clk.py --clk 0 40 python3 ./tb/shinTest/gen_sim_cdr_clk.py ${CDRCLK}
iverilog -Wall \ iverilog -Wall \
-o ./tb/build/simCDR.iverilog \ -o ./tb/build/simCDR.iverilog \
-y ./generated/SimCDR \ -y ./generated/SimCDR \