diff --git a/Makefile b/Makefile
index 8e88c0d..3231bba 100644
--- a/Makefile
+++ b/Makefile
@@ -5,6 +5,12 @@ ISR_MARCH=-march=rv32i -mabi=ilp32
 APP_MARCH=-march=rv32i -mabi=ilp32
 ISR_CFLAGS=-O2
 APP_CFLAGS=-O2
+
+SPI_TYPE ?= -spi 0
+TRANS_CODE ?= 
+DEVCLK ?= --dev1 0 90 --dev2 0 -90
+CDRCLK ?= --clk 0 40
+
 ifeq "$(RVCCVERSION)" "12.2.0"
    	ISR_MARCH=-march=rv32izicsr -mabi=ilp32
 	APP_MARCH=-march=rv32izicsr -mabi=ilp32
@@ -12,31 +18,13 @@ endif
 
 .PHONY: compile tb wave
 
-
-
-
-
 shin:
 	rm -f ./generated/shin/*
 	rm -f ./generated/SimCDR/*
 	sbt "test:runMain test.testShinModule"
 
 testShin:
-	python3 ./tb/shinTest/gen_pkt.py
-	mkdir -p generated/log
-	rm -rf generated/log/*
-	iverilog -Wall  \
-	-o ./tb/build/shinTest.iverilog  \
-	-y ./generated/shin \
-	-I ./generated/shin \
-	-D RANDOMIZE_REG_INIT \
-	-D IVERILOG_COMPILE \
-	./tb/shinTest/ShinTopSpiTb.v 
-	vvp  -N ./tb/build/shinTest.iverilog -lxt2 -fst || true
-	python3 ./tb/shinTest/check_testcase.py
-
-testShin8b10b:
-	python3 ./tb/shinTest/gen_pkt.py -8b10b
+	python3 ./tb/shinTest/gen_pkt.py ${SPI_TYPE} ${TRANS_CODE}
 	mkdir -p generated/log
 	rm -rf generated/log/*
 	iverilog -Wall  \
@@ -50,7 +38,7 @@ testShin8b10b:
 	python3 ./tb/shinTest/check_testcase.py
 
 testShinClk:
-	python3 ./tb/shinTest/gen_pkt_clk.py --dev1 0 92 --dev2 0 -92 -8b10b
+	python3 ./tb/shinTest/gen_pkt_clk.py ${DEVCLK} ${SPI_TYPE} ${TRANS_CODE}
 	mkdir -p generated/log
 	rm -rf generated/log/*
 	iverilog -Wall  \
@@ -64,7 +52,7 @@ testShinClk:
 	python3 ./tb/shinTest/check_testcase.py
 
 testCDR:
-	python3 ./tb/shinTest/gen_sim_cdr_clk.py --clk 0 40
+	python3 ./tb/shinTest/gen_sim_cdr_clk.py ${CDRCLK}
 	iverilog -Wall  \
 	-o ./tb/build/simCDR.iverilog  \
 	-y ./generated/SimCDR \