修改Makefile的模拟策略
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30
Makefile
30
Makefile
@@ -5,6 +5,12 @@ ISR_MARCH=-march=rv32i -mabi=ilp32
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APP_MARCH=-march=rv32i -mabi=ilp32
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APP_MARCH=-march=rv32i -mabi=ilp32
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ISR_CFLAGS=-O2
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ISR_CFLAGS=-O2
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APP_CFLAGS=-O2
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APP_CFLAGS=-O2
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SPI_TYPE ?= -spi 0
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TRANS_CODE ?=
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DEVCLK ?= --dev1 0 90 --dev2 0 -90
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CDRCLK ?= --clk 0 40
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ifeq "$(RVCCVERSION)" "12.2.0"
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ifeq "$(RVCCVERSION)" "12.2.0"
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ISR_MARCH=-march=rv32izicsr -mabi=ilp32
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ISR_MARCH=-march=rv32izicsr -mabi=ilp32
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APP_MARCH=-march=rv32izicsr -mabi=ilp32
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APP_MARCH=-march=rv32izicsr -mabi=ilp32
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@@ -12,31 +18,13 @@ endif
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.PHONY: compile tb wave
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.PHONY: compile tb wave
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shin:
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shin:
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rm -f ./generated/shin/*
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rm -f ./generated/shin/*
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rm -f ./generated/SimCDR/*
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rm -f ./generated/SimCDR/*
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sbt "test:runMain test.testShinModule"
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sbt "test:runMain test.testShinModule"
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testShin:
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testShin:
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python3 ./tb/shinTest/gen_pkt.py
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python3 ./tb/shinTest/gen_pkt.py ${SPI_TYPE} ${TRANS_CODE}
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mkdir -p generated/log
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rm -rf generated/log/*
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iverilog -Wall \
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-o ./tb/build/shinTest.iverilog \
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-y ./generated/shin \
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-I ./generated/shin \
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-D RANDOMIZE_REG_INIT \
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-D IVERILOG_COMPILE \
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./tb/shinTest/ShinTopSpiTb.v
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vvp -N ./tb/build/shinTest.iverilog -lxt2 -fst || true
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python3 ./tb/shinTest/check_testcase.py
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testShin8b10b:
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python3 ./tb/shinTest/gen_pkt.py -8b10b
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mkdir -p generated/log
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mkdir -p generated/log
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rm -rf generated/log/*
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rm -rf generated/log/*
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iverilog -Wall \
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iverilog -Wall \
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@@ -50,7 +38,7 @@ testShin8b10b:
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python3 ./tb/shinTest/check_testcase.py
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python3 ./tb/shinTest/check_testcase.py
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testShinClk:
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testShinClk:
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python3 ./tb/shinTest/gen_pkt_clk.py --dev1 0 92 --dev2 0 -92 -8b10b
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python3 ./tb/shinTest/gen_pkt_clk.py ${DEVCLK} ${SPI_TYPE} ${TRANS_CODE}
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mkdir -p generated/log
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mkdir -p generated/log
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rm -rf generated/log/*
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rm -rf generated/log/*
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iverilog -Wall \
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iverilog -Wall \
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@@ -64,7 +52,7 @@ testShinClk:
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python3 ./tb/shinTest/check_testcase.py
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python3 ./tb/shinTest/check_testcase.py
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testCDR:
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testCDR:
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python3 ./tb/shinTest/gen_sim_cdr_clk.py --clk 0 40
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python3 ./tb/shinTest/gen_sim_cdr_clk.py ${CDRCLK}
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iverilog -Wall \
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iverilog -Wall \
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-o ./tb/build/simCDR.iverilog \
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-o ./tb/build/simCDR.iverilog \
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-y ./generated/SimCDR \
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-y ./generated/SimCDR \
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