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修正：单写单读从站写入访问时序问题

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This commit is contained in:
Ruige Lee
2025-05-16 14:51:52 +08:00
parent f20efe5b25
commit d5db3aebdb
1 changed files with 14 additions and 14 deletions
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28
src/main/scala/backBoard/shin/SlaveParser.scala
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@@ -406,27 +406,27 @@ trait SlaveParserRW{ this: SlaveParserBase =>
when( downRecParser.io.subMsgReq.fire & downRecParser.io.subMsgReq.bits.devIndex === localDevIndex ){ when( downRecParser.io.subMsgReq.fire & downRecParser.io.subMsgReq.bits.devIndex === localDevIndex ){
addrw := downRecParser.io.subMsgReq.bits.address addrw := downRecParser.io.subMsgReq.bits.address
} .elsewhen( isWrite ){ } .elsewhen( isWrite & downRecParser.io.data.fire ){
addrw := addrw + 1.U addrw := addrw + 1.U
} }
io.lvds.isEnW := isWrite & isWRReg io.lvds.isEnW := isWrite & isWRReg & downRecParser.io.data.fire
io.lvds.dataw := downRecParser.io.data.bits io.lvds.dataw := downRecParser.io.data.bits
io.sram_w(0).enw := isWrite & isWRSM0 io.sram_w(0).enw := isWrite & isWRSM0 & downRecParser.io.data.fire
io.sram_w(0).addrw := addrw(10,0) io.sram_w(0).addrw := addrw(10,0)
io.sram_w(0).dataw := downRecParser.io.data.bits io.sram_w(0).dataw := downRecParser.io.data.bits
io.sram_w(1).enw := isWrite & isWRSM2 io.sram_w(1).enw := isWrite & isWRSM2 & downRecParser.io.data.fire
io.sram_w(1).addrw := addrw(10,0) io.sram_w(1).addrw := addrw(10,0)
io.sram_w(1).dataw := downRecParser.io.data.bits io.sram_w(1).dataw := downRecParser.io.data.bits
io.sram_w(2).enw := isWrite & isWRSM4 io.sram_w(2).enw := isWrite & isWRSM4 & downRecParser.io.data.fire
io.sram_w(2).addrw := addrw(10,0) io.sram_w(2).addrw := addrw(10,0)
io.sram_w(2).dataw := downRecParser.io.data.bits io.sram_w(2).dataw := downRecParser.io.data.bits
io.sram_w(3).enw := isWrite & isWRSM6 io.sram_w(3).enw := isWrite & isWRSM6 & downRecParser.io.data.fire
io.sram_w(3).addrw := addrw(10,0) io.sram_w(3).addrw := addrw(10,0)
io.sram_w(3).dataw := downRecParser.io.data.bits io.sram_w(3).dataw := downRecParser.io.data.bits
@@ -480,7 +480,7 @@ trait SlaveParserRW{ this: SlaveParserBase =>
when( upRecParser.io.subMsgReq.fire & upRecParser.io.subMsgReq.bits.devIndex === localDevIndex ){ when( upRecParser.io.subMsgReq.fire & upRecParser.io.subMsgReq.bits.devIndex === localDevIndex ){
addrr := upRecParser.io.subMsgReq.bits.address addrr := upRecParser.io.subMsgReq.bits.address
} .elsewhen( isRead ){ } .elsewhen( isRead & upRecParser.io.data.fire ){
addrr := addrr + 1.U addrr := addrr + 1.U
} }
@@ -513,20 +513,20 @@ trait SlaveParserRW{ this: SlaveParserBase =>
} }
io.lvds.isEnR := isRead & isRDReg io.lvds.isEnR := isRead & isRDReg & ( upRecParser.io.subMsgReq.fire | upRecParser.io.data.fire )
io.lvds.addrSel := Mux1H(Seq( io.lvds.addrSel := Mux1H(Seq(
isRead -> readSMAddr(10,0) isRead -> readSMAddr(10,0),
isWrite -> addrw(10,0) isWrite -> addrw(10,0),
)) ))
assert( ~(isRead & isWrite) ) assert( ~(isRead & isWrite) )
io.sram_r(0).enr := isRead & isRDSM1 io.sram_r(0).enr := isRead & isRDSM1 & ( upRecParser.io.subMsgReq.fire | upRecParser.io.data.fire )
io.sram_r(1).enr := isRead & isRDSM3 io.sram_r(1).enr := isRead & isRDSM3 & ( upRecParser.io.subMsgReq.fire | upRecParser.io.data.fire )
io.sram_r(2).enr := isRead & isRDSM5 io.sram_r(2).enr := isRead & isRDSM5 & ( upRecParser.io.subMsgReq.fire | upRecParser.io.data.fire )
io.sram_r(3).enr := isRead & isRDSM7 io.sram_r(3).enr := isRead & isRDSM7 & ( upRecParser.io.subMsgReq.fire | upRecParser.io.data.fire )
io.sram_r(0).addrr := readSMAddr(10,0) io.sram_r(0).addrr := readSMAddr(10,0)
io.sram_r(1).addrr := readSMAddr(10,0) io.sram_r(1).addrr := readSMAddr(10,0)