From d5db3aebdb06a50f8fca6649504eb8a7728c22d9 Mon Sep 17 00:00:00 2001
From: Ruige Lee <wut.ruigeli@gmail.com>
Date: Fri, 16 May 2025 14:51:52 +0800
Subject: [PATCH] =?UTF-8?q?=E4=BF=AE=E6=AD=A3=EF=BC=9A=E5=8D=95=E5=86=99?=
 =?UTF-8?q?=E5=8D=95=E8=AF=BB=E4=BB=8E=E7=AB=99=E5=86=99=E5=85=A5=E8=AE=BF?=
 =?UTF-8?q?=E9=97=AE=E6=97=B6=E5=BA=8F=E9=97=AE=E9=A2=98?=
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---
 .../scala/backBoard/shin/SlaveParser.scala    | 28 +++++++++----------
 1 file changed, 14 insertions(+), 14 deletions(-)

diff --git a/src/main/scala/backBoard/shin/SlaveParser.scala b/src/main/scala/backBoard/shin/SlaveParser.scala
index cb90c5d..4253fce 100644
--- a/src/main/scala/backBoard/shin/SlaveParser.scala
+++ b/src/main/scala/backBoard/shin/SlaveParser.scala
@@ -406,27 +406,27 @@ trait SlaveParserRW{ this: SlaveParserBase =>
 
   when( downRecParser.io.subMsgReq.fire & downRecParser.io.subMsgReq.bits.devIndex === localDevIndex ){
     addrw := downRecParser.io.subMsgReq.bits.address
-  } .elsewhen( isWrite ){
+  } .elsewhen( isWrite & downRecParser.io.data.fire ){
     addrw := addrw + 1.U
   }
 
 
-  io.lvds.isEnW   := isWrite & isWRReg
+  io.lvds.isEnW   := isWrite & isWRReg & downRecParser.io.data.fire
   io.lvds.dataw   := downRecParser.io.data.bits
 
-  io.sram_w(0).enw   := isWrite & isWRSM0
+  io.sram_w(0).enw   := isWrite & isWRSM0 & downRecParser.io.data.fire
   io.sram_w(0).addrw := addrw(10,0)
   io.sram_w(0).dataw := downRecParser.io.data.bits
 
-  io.sram_w(1).enw   := isWrite & isWRSM2
+  io.sram_w(1).enw   := isWrite & isWRSM2 & downRecParser.io.data.fire
   io.sram_w(1).addrw := addrw(10,0)
   io.sram_w(1).dataw := downRecParser.io.data.bits
 
-  io.sram_w(2).enw   := isWrite & isWRSM4
+  io.sram_w(2).enw   := isWrite & isWRSM4 & downRecParser.io.data.fire
   io.sram_w(2).addrw := addrw(10,0)
   io.sram_w(2).dataw := downRecParser.io.data.bits
 
-  io.sram_w(3).enw   := isWrite & isWRSM6
+  io.sram_w(3).enw   := isWrite & isWRSM6 & downRecParser.io.data.fire
   io.sram_w(3).addrw := addrw(10,0)
   io.sram_w(3).dataw := downRecParser.io.data.bits
 
@@ -480,7 +480,7 @@ trait SlaveParserRW{ this: SlaveParserBase =>
 
   when( upRecParser.io.subMsgReq.fire & upRecParser.io.subMsgReq.bits.devIndex === localDevIndex ){
     addrr := upRecParser.io.subMsgReq.bits.address
-  } .elsewhen( isRead ){
+  } .elsewhen( isRead & upRecParser.io.data.fire ){
     addrr := addrr + 1.U
   }
 
@@ -513,20 +513,20 @@ trait SlaveParserRW{ this: SlaveParserBase =>
 
   }
 
-  io.lvds.isEnR   := isRead & isRDReg
+  io.lvds.isEnR   := isRead & isRDReg & ( upRecParser.io.subMsgReq.fire | upRecParser.io.data.fire )
   io.lvds.addrSel := Mux1H(Seq(
-    isRead  -> readSMAddr(10,0)
-    isWrite -> addrw(10,0)
+    isRead  -> readSMAddr(10,0),
+    isWrite -> addrw(10,0),
   ))
   assert( ~(isRead & isWrite) )
   
 
 
 
-  io.sram_r(0).enr := isRead & isRDSM1
-  io.sram_r(1).enr := isRead & isRDSM3
-  io.sram_r(2).enr := isRead & isRDSM5
-  io.sram_r(3).enr := isRead & isRDSM7
+  io.sram_r(0).enr := isRead & isRDSM1 & ( upRecParser.io.subMsgReq.fire | upRecParser.io.data.fire )
+  io.sram_r(1).enr := isRead & isRDSM3 & ( upRecParser.io.subMsgReq.fire | upRecParser.io.data.fire )
+  io.sram_r(2).enr := isRead & isRDSM5 & ( upRecParser.io.subMsgReq.fire | upRecParser.io.data.fire )
+  io.sram_r(3).enr := isRead & isRDSM7 & ( upRecParser.io.subMsgReq.fire | upRecParser.io.data.fire )
 
   io.sram_r(0).addrr := readSMAddr(10,0)
   io.sram_r(1).addrr := readSMAddr(10,0)