代码整理

src/main/scala/backBoard/shin/Interface.scala

@@ -255,8 +255,6 @@ abstract class InterfaceBase extends Module with RequireAsyncReset{
         (addr === ("h10".U(16.W) + i.U) ) -> cReg.uniCode( 8*i+7,8*i+0 )
       }) ++
 
-
-
       Seq(
         (addr === "h8".U )  -> cReg.busRate( 7,0 ),
         (addr === "h9".U )  -> cReg.spiSel,
@@ -264,25 +262,14 @@ abstract class InterfaceBase extends Module with RequireAsyncReset{
         (addr === "hb".U & isSlvMode)  -> sReg.localDevIndex(15,8),
       ) ++
 
-
       Seq(
         (addr === "h18".U )            -> sReg.lvdsWriteAble.extract(0),
         (addr === "h20".U & isMstMode) -> Cat(mReg.rxSM, mReg.txSM, 0.U(1.W) ),
         (addr === "h22".U & isMstMode) -> mReg.isRecCRCErr,
-                //(addr === "h21".U & isMstMode) -> mReg.txLength,
-
         (addr === "h24".U & isMstMode) -> mReg.rplTimeStampTx(7,0),
         (addr === "h25".U & isMstMode) -> mReg.rplTimeStampTx(15,8),
-
-
-
       ) ++
 
-
-
-
-
-
       Seq(
         (addr === "h40".U ) -> cReg.softResetCode(1),
         (addr === "h41".U ) -> cReg.softResetCode(1),
@@ -374,14 +361,9 @@ abstract class InterfaceBase extends Module with RequireAsyncReset{
         (addr === "hb6".U ) -> cReg.statUpRecByteCnt(55,48),
         (addr === "hb7".U ) -> cReg.statUpRecByteCnt(63,56),
 
-
-
-
         (addr === "hc0".U ) -> Cat( sReg.isDevOnRightModify, sReg.isDevOnRight, 0.U(3.W) ),
         (addr === "hc2".U ) -> sReg.indexOfRightDev(7,0),
         (addr === "hc3".U ) -> sReg.indexOfRightDev(13,8),
-        // (addr === "hc4".U ) -> sReg.indexOfLeftDev(7,0),
-        // (addr === "hc5".U ) -> sReg.indexOfLeftDev(13,8),
       ) ++
 
       Seq(
@@ -500,18 +482,12 @@ abstract class InterfaceBase extends Module with RequireAsyncReset{
       )}.reduce(_++_) ++
       ( 0 until 8 ).map{ i =>
         ( addr === ("h301".U(16.W) + (i*4).U) )  -> cReg.smUsedDepth(i)
-      } ++
-      ( 0 until 8 ).map{ i =>
         ( addr === ("h302".U(16.W) + (i*4).U) )  -> cReg.smTrigLen(i)(7,0)
-      } ++
-      ( 0 until 8 ).map{ i =>
         ( addr === ("h303".U(16.W) + (i*4).U) )  -> cReg.smTrigLen(i)(10,8)
       } ++
 
       ( 0 until 4 ).map{ i =>
         ( addr === ("h400".U(16.W) + i.U) )  -> cReg.wdtStatus( 8*i+7, 8*i+0 )
-      } ++
-      ( 0 until 4 ).map{ i =>
         ( addr === ("h404".U(16.W) + i.U) )  -> cReg.wdtEnable( 8*i+7, 8*i+0 )
       } ++
       (for( i <- 0 until 17; j <- 0 until 4 ) yield {
@@ -525,26 +501,12 @@ abstract class InterfaceBase extends Module with RequireAsyncReset{
       ) ++
       ( 0 until 8 ).map{ i =>
         ( addr === ("h508".U(16.W) + i.U) )  -> cReg.event.posedgeTimeStampLatch(0)( 8*i+7, 8*i+0 )
-      } ++
-      ( 0 until 8 ).map{ i =>
         ( addr === ("h510".U(16.W) + i.U) )  -> cReg.event.negedgeTimeStampLatch(0)( 8*i+7, 8*i+0 )
-      } ++
-      ( 0 until 8 ).map{ i =>
         ( addr === ("h518".U(16.W) + i.U) )  -> cReg.event.posedgeTimeStampLatch(1)( 8*i+7, 8*i+0 )
-      } ++
-      ( 0 until 8 ).map{ i =>
         ( addr === ("h520".U(16.W) + i.U) )  -> cReg.event.negedgeTimeStampLatch(1)( 8*i+7, 8*i+0 )
-      } ++
-      ( 0 until 8 ).map{ i =>
         ( addr === ("h528".U(16.W) + i.U) )  -> cReg.event.mcuSMTimeStampEnq( 8*i+7, 8*i+0 )
-      } ++
-      ( 0 until 8 ).map{ i =>
         ( addr === ("h530".U(16.W) + i.U) )  -> cReg.event.mcuSMTimeStampDeq( 8*i+7, 8*i+0 )
-      } ++
-      ( 0 until 8 ).map{ i =>
         ( addr === ("h538".U(16.W) + i.U) )  -> cReg.event.lvdsSMTimeStampEnq( 8*i+7, 8*i+0 )
-      } ++
-      ( 0 until 8 ).map{ i =>
         ( addr === ("h540".U(16.W) + i.U) )  -> cReg.event.lvdsSMTimeStampDeq( 8*i+7, 8*i+0 )
       } ++
       Seq()
@@ -569,12 +531,6 @@ abstract class InterfaceBase extends Module with RequireAsyncReset{
 
 trait InterfaceMCUop{ this: InterfaceBase =>
 
-
-
-
-
-
-
   isEnW := Mux1H(Seq(
     ( cReg.spiSel === 0.U ) -> iQSpi.io.isEnW,
     ( cReg.spiSel === 1.U ) ->  oSpi.io.isEnW,
@@ -638,7 +594,6 @@ trait InterfaceMCUop{ this: InterfaceBase =>
 
   mReg.txSM     := RegEnable( dataw(2,1), 0.U(2.W), isEnW & addrw === "h20".U )
   mReg.rxSM     := RegEnable( dataw(4,3), 0.U(2.W), isEnW & addrw === "h20".U )
-  // mReg.txLength := Cat( RegEnable( dataw, 0.U, isEnW & addrw === "h22".U ), RegEnable( dataw, 0.U, isEnW & addrw === "h21".U ) )
 
   val mReg_isRecCRCErr = RegInit(0.U(4.W))
   mReg.isRecCRCErr := mReg_isRecCRCErr
@@ -680,7 +635,6 @@ trait InterfaceCheckSM{ this: InterfaceBase =>
 
 
   for( i <- 0 until 8 ){
-
     io.isSMReset(i) := isEnW & (addrw === ("h300".U(16.W) + (i*4).U))
 
     cReg.smUsedDepth(i) := io.smUsedDepth(i)
@@ -699,10 +653,6 @@ trait InterfaceCheckSM{ this: InterfaceBase =>
         smTrigLen_L(i) := io.lvds.dataw
       }
     }
-
-
-
-
   }
 
 
@@ -746,8 +696,6 @@ trait InterfaceEBMMU{ this: InterfaceBase =>
   
   io.lvds.datar := RegEnable(AcquireReg(addr = io.lvds.addrr), 0.U(8.W), io.lvds.isEnR)
 
-  
-
   ( 0 until 16 ).map{ i =>
     sReg.ebmmu(i).lAddr := Cat(
       RegEnable( io.lvds.dataw(5,0), 0.U(8.W), sReg.isLVDSWriteAble & io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h203".U(16.W) + (10*i).U )) ),
@@ -1145,9 +1093,6 @@ trait InterfaceInterrupt{ this: InterfaceBase =>
     intStatus(4) := true.B
   }
 
-
-
-
   //从站SM请求
   for( i <- 0 until 8 ){
     when( io.intSlvTrig(i) ){
@@ -1398,11 +1343,6 @@ trait InterfaceStat{ this: InterfaceBase =>
     statDownRecByteCnt := statDownRecByteCnt + 1.U
   }
 
-
-
-
-
-
   when(io.lvds.isEnW & (io.lvds.addrw === "ha0".U )){
     statUpRecErrorCnt := 0.U
   } .elsewhen( io.upRecStat.isRecError ){
@@ -1475,10 +1415,7 @@ with InterfaceAnalog
 
   io.txReq.bits.txSM  := mReg.txSM
   io.txReq.bits.rxSM  := mReg.rxSM
-  // io.txReq.bits.txLength := //mReg.txLength
+  io.txReq.valid := RegNext(isEnW & addrw === "h20".U & dataw.extract(0) === "b1".U, false.B)
-  io.txReq.valid := RegNext(isEnW & addrw === "h20".U & dataw.extract(0) === "b1".U, false.B) //& mReg.txLength =/= 0.U
-
-
 
 
   sReg.localDevIndex := io.localDevIndex
@@ -1487,6 +1424,5 @@ with InterfaceAnalog
   sReg.isDevOnRightModify := io.isDevOnRightModify
   sReg.indexOfRightDev    := io.indexOfRightDev
 
-
-
 }
+

src/main/scala/backBoard/shin/MasterParser.scala

@@ -43,11 +43,6 @@ abstract class MasterParserBase extends Module with RequireAsyncReset{
   val txcrc = Module(new crc32_8)
   val rxcrc = Module(new crc32_8)
 
-
-
-
-  // io.req.ready := reqReady
-
   when( io.req ){
     reqReady := false.B
   } .elsewhen( io.downOut.fire & txCnt === txLen + (4-1).U ){
@@ -134,8 +129,6 @@ abstract class MasterParserBase extends Module with RequireAsyncReset{
   io.downOut.bits.tuser := false.B 
   io.downOut.bits.tlast := txCnt === (txLen + 3.U)
 
-
-
   val recCrcCheck = RegInit(0.U(32.W))
 
   when( io.req ){
@@ -154,16 +147,10 @@ abstract class MasterParserBase extends Module with RequireAsyncReset{
 
   io.rsp.valid := io.upIn.fire & io.upIn.bits.tlast
   io.rsp.bits.isError := io.upIn.fire & io.upIn.bits.tlast & (Cat( recCrcCheck(31,8), io.upIn.bits.tdata ) =/= rxcrc.io.crc)
-  // io.rsp.bits.length  := rxCnt + 1.U
-
-
 
   io.rxEnq := io.upIn.fire    & io.upIn.bits.tlast
   io.txDeq := io.downOut.fire & io.downOut.bits.tlast
 
-
-
-
   txcrc.io.isEnable := io.downOut.fire & txCnt < txLen
   txcrc.io.dataIn   := io.downOut.bits.tdata
   txcrc.io.flush    := reqReady
@@ -172,8 +159,6 @@ abstract class MasterParserBase extends Module with RequireAsyncReset{
   rxcrc.io.dataIn   := io.upIn.bits.tdata
   rxcrc.io.flush    := io.rsp.fire
 
-
-
   when( io.upIn.fire ){
     when( rxCnt === rxLen ){
       recCrcCheck := io.upIn.bits.tdata << 24
@@ -199,7 +184,6 @@ trait MasterParserStat{ this: MasterParserBase =>
   io.upRecStat.isFinish         := io.rsp.valid & ~io.rsp.bits.isError
   io.upRecStat.isRecByteAck     := io.upIn.fire
 
-  
 }
 
 class MasterParser extends MasterParserBase

src/main/scala/backBoard/shin/MstSlvSwitch.scala

@@ -352,9 +352,6 @@ trait MstSlvSwitchMaster{ this: MstSlvSwitchBase =>
   }
 
   masterParser.io.req         := interface.io.txReq.valid
-  // masterParser.io.req.bits.txLength := interface.io.txReq.bits.txLength
-
-  // io.rsp := masterParser.io.rsp
 
   masterParser.io.cReg := interface.io.cReg
   masterParser.io.mReg := interface.io.mReg
@@ -440,9 +437,6 @@ trait MstSlvSwitchSlave{ this: MstSlvSwitchBase =>
   interface.io.localDevIndex := slaveParser.io.localDevIndex
 
   //从站链路寄存器
-  // interface.io.isDevOnLeft := slaveParser.io.isDevOnLeft
-  // interface.io.isDevOnLeftModify := slaveParser.io.isDevOnLeftModify
-  // interface.io.indexOfLeftDev := slaveParser.io.indexOfLeftDev
   interface.io.isDevOnRight := slaveParser.io.isDevOnRight
   interface.io.isDevOnRightModify := slaveParser.io.isDevOnRightModify
   interface.io.indexOfRightDev := slaveParser.io.indexOfRightDev
@@ -627,12 +621,6 @@ trait MstSlvSwitchCDRIn{ this: MstSlvSwitchBase =>
   val cdrSelC = interface.io.cReg.cdrParam === 2.U
   val cdrSelA = ~cdrSelB & ~cdrSelC
 
-  // val downCDRSampleIn = Vec(3, Flipped(new CDRInSampleIO) )
-  // val upCDRSampleIn   = Vec(3, Flipped(new CDRInSampleIO) )
-
-
-
-
   when(cdrSelB){
     io.downCDRSampleIn(1).serDat := downInSerDat
     io.upCDRSampleIn(1).serDat   := upInSerDat

src/main/scala/backBoard/shin/NSpiInterface.scala.bk

@@ -1,147 +0,0 @@
-package BACK
-
-import chisel3._
-import chisel3.util._
-
-
-
-abstract class SyncSpiInterfaceBase extends Module with RequireAsyncReset{
-  val io = IO(new RegAccessInterfaceIO)
-
-}
-
-class SyncSSpiInterface extends SyncSpiInterfaceBase{
-  val spi = IO(new SSPIInterfaceIO)
-
-  // withClockAndReset(sck.asClock, reset.asBool){
-   
-
-
-  spi.miso := exRego.extract(7)
-
-  val bitSel  = withClockAndReset(spi.sck.asClock, spi.csn){RegInit(0.U(3.W)) }
-  val byteSel = withClockAndReset(spi.sck.asClock, spi.csn){RegInit(0.U(12.W))}
-  val exRego  = withClockAndReset(spi.sck.asClock, spi.csn){RegInit(0.U(8.W))}
-  val exRegi  = withClockAndReset(spi.sck.asClock, spi.csn){RegInit(0.U(8.W))}
-
-
-
-  when( true.B ){
-    bitSel := bitSel + 1.U
-  }
-
-  when( bitSel.andR ){
-    byteSel := byteSel + 1.U
-  }
-
-  when( true.B ){
-    exRegi := Cat( exRegi(6 ,0), spi.mosi )
-  }
-
-
-  when( bitSel === 0.U ){
-    when((byteSel === 1.U || byteSel === 2.U) ){
-      exRego := 0.U //地址1，cmd
-    } .elsewhen( isSpiRead ){
-      exRego := datar_async
-    }
-  }.otherwise{
-    exRego := exRego << 1
-  }
-
-  val addrw_async = withClockAndReset(spi.sck.asClock, spi.csn){ RegInit(0.U(16.W)) }
-  val addrr_async = withClockAndReset(spi.sck.asClock, spi.csn){ RegInit(0.U(16.W)) }
-  val dataw_async = withClockAndReset(spi.sck.asClock, spi.csn){ RegInit(0.U(8.W)) }
-  val datar_async = withClockAndReset(spi.sck.asClock, spi.csn){ RegInit(0.U(8.W)) }
-  val spiCmd      = withClockAndReset(spi.sck.asClock, spi.csn){ RegInit(false.B) }
-  val isSpiWrite = ~spiCmd
-  val isSpiRead  =  spiCmd
-
-  when( bitSel === 0.U ){
-    when( byteSel === 1.U ){
-      addrw_async := exRegi
-    } .elsewhen( byteSel === 2.U ) {
-      addrw_async := Cat(addrw_async(7,0), exRegi)
-    } .elsewhen( byteSel > 3.U ){
-      addrw_async := addrw_async + 1.U
-    }    
-  }
-
-  when( bitSel === 0.U ){
-    when( byteSel === 1.U ){
-      addrr_async := exRegi
-    } .elsewhen( byteSel === 2.U ) {
-      addrr_async := Cat(addrr_async(7,0), exRegi)
-    } .elsewhen( byteSel > 2.U ){
-      addrr_async := addrr_async + 1.U
-    }    
-  }
-
-  when( byteSel === 2.U & bitSel === 0.U ){ //CS为低，且SCK上跳的第0byte
-    spiCmd := spi.mosi
-  }
-
-
-
-  when( bitSel === 0.U ){
-    when( byteSel > 3.U & isSpiWrite ){
-      dataw_async := exRegi
-    }    
-  }
-
-
-
-  io.dataw := exRegi
-  io.addrr := Mux( isSpiRead, addrr + 1.U, addrr )
-
-  // io.addrSel :=
-  //   Mux( isSpiRead, addrSel + 1.U, addrSel )//覆盖三种情况
-  // val readData = RegEnable(io.datar, io.isEnR)
-  
-
-  isEnW_async
-  isEnR_async
-  addrw_async
-  addrr_async
-  datar_async
-  dataw_async
-
-
-  // isEnR_async := bitSel === 1.U & (byteSel >= 2.U) & isSpiRead
-  // isEnW_async := bitSel === 0.U & (byteSel >= 4.U) & isSpiWrite
-
-  val isEnWSet_async   = withClockAndReset(spi.sck.asClock, spi.csn){ RegInit(false.B) }
-  val isEnWSet_sync    = ShiftRegisters(isEnWSet_async, 3, false.B, true.B)
-  val isEnWReset_async = withClockAndReset(spi.sck.asClock, spi.csn){ ShiftRegister(isEnWSet_sync(1), 2, false.B, true.B) }
-
-  when( bitSel === 0.U & (byteSel >= 4.U) & isSpiWrite ){
-    assert( ~isEnWSet_async, "Assert Failed @spi!\n" )
-    isEnWSet_async := true.B
-  } .elsewhen(isEnWReSet_async){
-    isEnWSet_async := false.B
-  }
-  
-  io.isEnW := ~isEnWSet_async(2) & isEnWSet_async(1)
-  io.addrw := addrw_async
-  io.dataw := dataw_async
-
-
-  val isEnRSet_async   = withClockAndReset(spi.sck.asClock, spi.csn){ RegInit(false.B) }
-  val isEnRSet_sync    = ShiftRegisters(isEnRSet_async, 3, false.B, true.B)
-  val isEnRReset_async = withClockAndReset(spi.sck.asClock, spi.csn){ ShiftRegister(isEnRSet_sync(1), 2, false.B, true.B) }
-
-  when( bitSel === 1.U & (byteSel >= 2.U) & isSpiRead ){
-    assert( ~isEnRSet_async, "Assert Failed @spi!\n" )
-    isEnRSet_async := true.B
-  } .elsewhen(isEnRReSet_async){
-    isEnRSet_async := false.B
-  }
-
-  io.isEnR := ~isEnRSet_async(2) & isEnRSet_async(1)
-  io.addrr := addrr_async
-  datar_async := withClockAndReset(spi.sck.asClock, spi.csn){ RegEnable(io.datar, 0.U, isEnRReSet_async }
-
-
-}
-
-

src/main/scala/backBoard/shin/ShareSRAM.scala

@@ -3,91 +3,6 @@ package BACK
 import chisel3._
 import chisel3.util._
 
-
-class ShareSRAMDP extends BlackBox with HasBlackBoxInline {
-
-  class ShareSRAMDPIO extends Bundle{
-
-      val addrA  = Input(UInt(15.W))
-      val datawA  = Input( UInt(8.W) )
-      val datarA  = Output( UInt(8.W) )
-      val enwA    = Input(Bool())
-      val enrA    = Input(Bool())
-      val clockA  = Input(Bool())
-
-
-      val addrB = Input(UInt(15.W))
-      val datawB = Input( UInt(8.W) )
-      val datarB = Output( UInt(8.W) )
-      val enwB   = Input(Bool())
-      val enrB   = Input(Bool())
-      val clockB = Input(Bool())
-
-  }
-  val io: ShareSRAMDPIO = IO(new ShareSRAMDPIO)
-
- setInline("ShareSRAMDP.v",
-              """
-      | module ShareSRAMDP(
-      |  	input [7:0]  datawA,
-      |  	input [14:0]   addrA,
-      |  	input enwA,
-      |  	input enrA,
-      |  	output [7:0] datarA,
-      |  	input clockA,
-      |
-      |  	input [7:0]  datawB,
-      |  	input [14:0]   addrB,
-      |  	input enwB,
-      |  	input enrB,
-      |  	output [7:0] datarB,
-      |  	input clockB
-      |  );
-      |  
-      |  reg [7:0] mem[0:32767];
-      |  reg [7:0] data_outa_reg = 8'b0;
-      |  reg [7:0] data_outb_reg = 8'b0;
-      |
-      |  assign datarA = data_outa_reg;
-      |  assign datarB = data_outb_reg;
-      |
-      |  always@( posedge clockA ) begin
-      |    if( enrA ) begin
-      |    end
-      |
-      |    if( enwA ) begin
-      |      mem[addrA] <= datawA;
-      |    end else begin
-      |      data_outa_reg <= mem[addrA];
-      |    end
-      |  end
-      |
-      |
-      |  always@( posedge clockB ) begin
-      |    if(enrB) begin
-      |    end
-      |
-      |    if( enwB ) begin
-      |      mem[addrB] <= datawB;
-      |    end else begin
-      |      data_outb_reg <= mem[addrB];
-      |    end
-      |  end
-      |
-      |  initial begin
-      |     for( integer i = 0; i < 32768; i = i + 1 ) begin
-      |       mem[i] = $random;
-      |     end
-      |  end
-      |
-      |
-      |endmodule
-    """.stripMargin)
-}
-
-
-
-
 class ShareSRAM2k extends BlackBox with HasBlackBoxInline {
 
   class ShareSRAM2kIO extends Bundle{

src/main/scala/backBoard/shin/SlaveParser.scala

@@ -26,17 +26,6 @@ class SubMsgTail extends Bundle{
   val workCnt  = UInt(16.W) //子报文工作计数
 }
 
-
-// class ShareSRAMIO extends Bundle{
-//   val addr  = Input(UInt(15.W))
-//   val dataw  = Input( UInt(8.W) )
-//   val datar  = Output( UInt(8.W) )
-//   val enw    = Input(Bool())
-//   val enr    = Input(Bool())
-// }
-
-
-
 class SlaveParserIO extends Bundle{
   val downIn  = Flipped( Decoupled(new AXIS_Bundle(8)) )
   val downOut = Decoupled(new AXIS_Bundle(8))
@@ -56,9 +45,6 @@ class SlaveParserIO extends Bundle{
   val localDevIndex = Output(UInt(16.W))
 
   //开放链路寄存器组给interface
-  // val isDevOnLeft        = Output(UInt(2.W))
-  // val isDevOnLeftModify  = Output(Bool())
-  // val indexOfLeftDev     = Output(UInt(14.W))
   val isDevOnRight       = Output(UInt(2.W))
   val isDevOnRightModify = Output(Bool())
   val indexOfRightDev    = Output(UInt(14.W))

src/main/scala/backBoard/shin/SlaveRecParser.scala

@@ -65,17 +65,9 @@ class SlaveRecParser extends Module with RequireAsyncReset{
   val FRAME_STYLE_COMMON = 0.U
   val FRAME_STYLE_PROBE  = 1.U
 
-
-
-
-
-
-
   val lengthCnt   = RegInit(0.U(12.W)) //动态计数器
   val frameLenCnt = RegInit(0.U(12.W)) //帧长度计数
 
-
-
   io.frameReq.valid := (stateCurr === STATE_HEADER) & (stateNext === STATE_SUBMSG_HEADER | stateNext === STATE_CRC)
   val frameHeader = RegInit(0.U.asTypeOf(new FrameHeader))
   io.frameReq.bits.frameLenAim := frameHeader.frameLenAim
@@ -172,12 +164,6 @@ class SlaveRecParser extends Module with RequireAsyncReset{
     }
   }
 
-
-
-
-
-
-
   stateNext := 
     Mux( io.flush, STATE_IDLE,
       Mux1H(Seq(
@@ -212,10 +198,6 @@ class SlaveRecParser extends Module with RequireAsyncReset{
       ))
     )
 
-
-
-
-
   io.stat.isHeaderError    := stateNext === STATE_ERROR & stateCurr === STATE_HEADER
   io.stat.isSubHeaderError := stateNext === STATE_ERROR & stateCurr === STATE_SUBMSG_HEADER
   io.stat.isPayloadError   := stateNext === STATE_ERROR & stateCurr === STATE_PAYLOAD_DATA

src/main/scala/backBoard/shin/SlaveSendGen.scala

@@ -12,15 +12,12 @@ class SubMsgTxInfo extends SubMsgHeader{
 class SlaveSendGenIO extends Bundle{
   val data = Vec(2, Flipped( Decoupled(UInt(8.W)) ) )
 
-
-
   val frameReq  = Flipped(Decoupled( new FrameHeader ))
   val subMsgHeadReq = Flipped(Decoupled( new SubMsgTxInfo ))
   val subMsgTailReq = Flipped(Decoupled( new SubMsgTail ))
 
   val send = Decoupled(new AXIS_Bundle(8))
 
-  val isError = Output(Bool())
   val stateCurr = Output(UInt(3.W))
 
   val flush = Input(Bool())
@@ -32,7 +29,6 @@ class SlaveSendGenIO extends Bundle{
 class SlaveSendGen extends Module with RequireAsyncReset{
   val io: SlaveSendGenIO = IO(new SlaveSendGenIO)
 
-
   val crc = Module(new crc32_8)
 
   val FRAME_STYLE_COMMON = 0.U
@@ -50,30 +46,19 @@ class SlaveSendGen extends Module with RequireAsyncReset{
   val stateNext = Wire(UInt(3.W))
   val stateCurr = RegNext(stateNext, STATE_IDLE); io.stateCurr := stateCurr
 
-  io.isError := false.B//stateCurr === STATE_ERROR
-
   crc.io.isEnable := io.send.fire & (
     stateCurr === STATE_FRAME_HEADER |
     stateCurr === STATE_SUBMSG_HEADER |
     stateCurr === STATE_SUBMSG_DATA   |
     stateCurr === STATE_SUBMSG_TAIL 
   )
-
-
-
-
   crc.io.flush := stateCurr === STATE_IDLE | io.flush
 
-
-
   val frameInfo = RegInit(0.U.asTypeOf(new FrameHeader))
 
   val subMsgHeadInfo = RegInit(0.U.asTypeOf(new SubMsgTxInfo))
   val subMsgTailInfo = RegInit(0.U.asTypeOf(new SubMsgTail))
 
-
-
-
   when( io.frameReq.fire ){
     frameInfo := io.frameReq.bits
   }
@@ -86,8 +71,6 @@ class SlaveSendGen extends Module with RequireAsyncReset{
     subMsgTailInfo := io.subMsgTailReq.bits
   }
 
-
-
   val lengthCnt   = RegInit(0.U(12.W))
   val frameLenCnt = RegInit(0.U(12.W))
 
@@ -99,15 +82,12 @@ class SlaveSendGen extends Module with RequireAsyncReset{
     }    
   }
 
-
   when( stateCurr =/= stateNext ){
     lengthCnt := 0.U
   } .elsewhen(io.send.fire){
     lengthCnt := lengthCnt + 1.U
   }
 
-
-
   io.frameReq.ready := true.B
   io.subMsgHeadReq.ready := stateCurr =/= STATE_SUBMSG_HEADER & stateNext === STATE_SUBMSG_HEADER
   io.subMsgTailReq.ready := stateCurr =/= STATE_SUBMSG_TAIL   & stateNext === STATE_SUBMSG_TAIL
@@ -137,7 +117,6 @@ class SlaveSendGen extends Module with RequireAsyncReset{
           ), STATE_SUBMSG_TAIL ),
 
         (stateCurr === STATE_CRC)           -> Mux( io.send.fire, Mux( lengthCnt === (4-1).U, STATE_IDLE, STATE_CRC ), STATE_CRC),
-        // (stateCurr === STATE_ERROR)         -> Mux( io.send.fire, STATE_IDLE, STATE_ERROR),
         (stateCurr === STATE_WAIT)          -> Mux( io.subMsgHeadReq.valid, STATE_SUBMSG_HEADER, STATE_WAIT),
       ))
     )
@@ -149,7 +128,6 @@ class SlaveSendGen extends Module with RequireAsyncReset{
   assert( ~(io.data(1).ready & ~io.data(1).valid) )
 
 
-
   io.send.valid := 
     (stateCurr === STATE_FRAME_HEADER)  |
     (stateCurr === STATE_SUBMSG_HEADER) |
@@ -157,7 +135,6 @@ class SlaveSendGen extends Module with RequireAsyncReset{
     (stateCurr === STATE_SUBMSG_TAIL) |
     (stateCurr === STATE_CRC)
 
-
   val tdata_frame_header = Mux1H(Seq(
     (lengthCnt === 0.U) -> frameInfo.frameLenAim(11,4),
     (lengthCnt === 1.U) -> Cat( frameInfo.frameLenAim(3,0), 0.U(2.W), frameInfo.frameStyle),
@@ -207,9 +184,7 @@ class SlaveSendGen extends Module with RequireAsyncReset{
     (stateCurr === STATE_CRC)           -> tdata_crc,
   ))
 
-  io.send.bits.tuser := false.B//(stateCurr === STATE_ERROR & stateNext === STATE_IDLE)
+  io.send.bits.tuser := false.B
-  io.send.bits.tlast := (stateCurr === STATE_CRC & stateNext === STATE_IDLE) //|| (stateCurr === STATE_ERROR & stateNext === STATE_IDLE)
+  io.send.bits.tlast := (stateCurr === STATE_CRC & stateNext === STATE_IDLE)
-
-
 
 }

src/main/scala/backBoard/shin/SpiInterface.scala

@@ -74,16 +74,6 @@ abstract class SpiInterfaceBase extends Module with RequireAsyncReset{
   }
 
 
-
-
-
-
-
-
-
-
-
-
 }
 
 class SSpiInterface extends SpiInterfaceBase{

src/main/scala/backBoard/shin/crc32.scala

@@ -4,73 +4,6 @@ import chisel3._
 import chisel3.util._
 
 
-// module eth_crc (Clk, Reset, Data, Enable, Initialize, Crc, CrcError);
-
-
-// input Clk;
-// input Reset;
-  // input [3:0] Data;
-  // input Enable;
-  // input Initialize;
-
-  // output [31:0] Crc;
-// output CrcError;
-
-// reg  [31:0] Crc;
-
-// wire [31:0] CrcNext;
-
-
-// assign CrcNext[0] = Enable & (Data[0] ^ Crc[28]); 
-// assign CrcNext[1] = Enable & (Data[1] ^ Data[0] ^ Crc[28] ^ Crc[29]); 
-// assign CrcNext[2] = Enable & (Data[2] ^ Data[1] ^ Data[0] ^ Crc[28] ^ Crc[29] ^ Crc[30]); 
-// assign CrcNext[3] = Enable & (Data[3] ^ Data[2] ^ Data[1] ^ Crc[29] ^ Crc[30] ^ Crc[31]); 
-// assign CrcNext[4] = (Enable & (Data[3] ^ Data[2] ^ Data[0] ^ Crc[28] ^ Crc[30] ^ Crc[31])) ^ Crc[0]; 
-// assign CrcNext[5] = (Enable & (Data[3] ^ Data[1] ^ Data[0] ^ Crc[28] ^ Crc[29] ^ Crc[31])) ^ Crc[1]; 
-// assign CrcNext[6] = (Enable & (Data[2] ^ Data[1] ^ Crc[29] ^ Crc[30])) ^ Crc[ 2]; 
-// assign CrcNext[7] = (Enable & (Data[3] ^ Data[2] ^ Data[0] ^ Crc[28] ^ Crc[30] ^ Crc[31])) ^ Crc[3]; 
-// assign CrcNext[8] = (Enable & (Data[3] ^ Data[1] ^ Data[0] ^ Crc[28] ^ Crc[29] ^ Crc[31])) ^ Crc[4]; 
-// assign CrcNext[9] = (Enable & (Data[2] ^ Data[1] ^ Crc[29] ^ Crc[30])) ^ Crc[5]; 
-// assign CrcNext[10] = (Enable & (Data[3] ^ Data[2] ^ Data[0] ^ Crc[28] ^ Crc[30] ^ Crc[31])) ^ Crc[6]; 
-// assign CrcNext[11] = (Enable & (Data[3] ^ Data[1] ^ Data[0] ^ Crc[28] ^ Crc[29] ^ Crc[31])) ^ Crc[7]; 
-// assign CrcNext[12] = (Enable & (Data[2] ^ Data[1] ^ Data[0] ^ Crc[28] ^ Crc[29] ^ Crc[30])) ^ Crc[8]; 
-// assign CrcNext[13] = (Enable & (Data[3] ^ Data[2] ^ Data[1] ^ Crc[29] ^ Crc[30] ^ Crc[31])) ^ Crc[9]; 
-// assign CrcNext[14] = (Enable & (Data[3] ^ Data[2] ^ Crc[30] ^ Crc[31])) ^ Crc[10]; 
-// assign CrcNext[15] = (Enable & (Data[3] ^ Crc[31])) ^ Crc[11]; 
-// assign CrcNext[16] = (Enable & (Data[0] ^ Crc[28])) ^ Crc[12]; 
-// assign CrcNext[17] = (Enable & (Data[1] ^ Crc[29])) ^ Crc[13]; 
-// assign CrcNext[18] = (Enable & (Data[2] ^ Crc[30])) ^ Crc[14]; 
-// assign CrcNext[19] = (Enable & (Data[3] ^ Crc[31])) ^ Crc[15]; 
-// assign CrcNext[20] = Crc[16]; 
-// assign CrcNext[21] = Crc[17]; 
-// assign CrcNext[22] = (Enable & (Data[0] ^ Crc[28])) ^ Crc[18]; 
-// assign CrcNext[23] = (Enable & (Data[1] ^ Data[0] ^ Crc[29] ^ Crc[28])) ^ Crc[19]; 
-// assign CrcNext[24] = (Enable & (Data[2] ^ Data[1] ^ Crc[30] ^ Crc[29])) ^ Crc[20]; 
-// assign CrcNext[25] = (Enable & (Data[3] ^ Data[2] ^ Crc[31] ^ Crc[30])) ^ Crc[21]; 
-// assign CrcNext[26] = (Enable & (Data[3] ^ Data[0] ^ Crc[31] ^ Crc[28])) ^ Crc[22]; 
-// assign CrcNext[27] = (Enable & (Data[1] ^ Crc[29])) ^ Crc[23]; 
-// assign CrcNext[28] = (Enable & (Data[2] ^ Crc[30])) ^ Crc[24]; 
-// assign CrcNext[29] = (Enable & (Data[3] ^ Crc[31])) ^ Crc[25]; 
-// assign CrcNext[30] = Crc[26]; 
-// assign CrcNext[31] = Crc[27]; 
-
-
-// always @ (posedge Clk or posedge Reset)
-// begin
-//   if (Reset)
-//     Crc <=  32'hffffffff;
-//   else
-//   if(Initialize)
-//     Crc <=  32'hffffffff;
-//   else
-//     Crc <=  CrcNext;
-// end
-
-// assign CrcError = Crc[31:0] != 32'hc704dd7b;  // CRC not equal to magic number
-
-// endmodule
-
-
 //-----------------------------------------------------------------------------
 // Copyright (C) 2009 OutputLogic.com
 // This source file may be used and distributed without restriction