From d46e06d5b0f18327eb15aa9c40a462a66ab4fbe3 Mon Sep 17 00:00:00 2001 From: RuigeLee Date: Thu, 11 Sep 2025 11:50:58 +0800 Subject: [PATCH] =?UTF-8?q?=E4=BB=A3=E7=A0=81=E6=95=B4=E7=90=86?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .../backBoard/{ebus => shin}/CDRIn.scala | 610 +++++++++--------- .../backBoard/{ebus => shin}/CDROut.scala | 234 +++---- .../backBoard/{ebus => shin}/Encryptor.scala | 0 src/main/scala/backBoard/shin/Interface.scala | 72 +-- .../scala/backBoard/shin/MasterParser.scala | 16 - .../scala/backBoard/shin/MstSlvSwitch.scala | 12 - .../backBoard/shin/NSpiInterface.scala.bk | 147 ----- src/main/scala/backBoard/shin/ShareSRAM.scala | 85 --- .../scala/backBoard/shin/SlaveParser.scala | 14 - .../scala/backBoard/shin/SlaveRecParser.scala | 18 - .../scala/backBoard/shin/SlaveSendGen.scala | 29 +- .../scala/backBoard/shin/SpiInterface.scala | 10 - .../scala/backBoard/{ebus => shin}/b4b5.scala | 156 ++--- .../backBoard/{ebus => shin}/b8b10.scala | 0 .../backBoard/{ebus => shin}/crc32.scala | 67 -- 15 files changed, 506 insertions(+), 964 deletions(-) rename src/main/scala/backBoard/{ebus => shin}/CDRIn.scala (96%) rename src/main/scala/backBoard/{ebus => shin}/CDROut.scala (96%) rename src/main/scala/backBoard/{ebus => shin}/Encryptor.scala (100%) delete mode 100644 src/main/scala/backBoard/shin/NSpiInterface.scala.bk rename src/main/scala/backBoard/{ebus => shin}/b4b5.scala (96%) rename src/main/scala/backBoard/{ebus => shin}/b8b10.scala (100%) rename src/main/scala/backBoard/{ebus => shin}/crc32.scala (62%) diff --git a/src/main/scala/backBoard/ebus/CDRIn.scala b/src/main/scala/backBoard/shin/CDRIn.scala similarity index 96% rename from src/main/scala/backBoard/ebus/CDRIn.scala rename to src/main/scala/backBoard/shin/CDRIn.scala index 63d396a..68f5836 100644 --- a/src/main/scala/backBoard/ebus/CDRIn.scala +++ b/src/main/scala/backBoard/shin/CDRIn.scala @@ -1,305 +1,305 @@ -package BACK - -import chisel3._ -import chisel3.util._ - - - -class CDRInSampleIO extends Bundle{ - val serDat = Input(Bool()) - val syncSerDat = Output(Bool()) -} - - -class CDRInMultiSample extends Module with RequireAsyncReset{ - val io: CDRInSampleIO = IO(new CDRInSampleIO) - val clkNum: Int = 16 - require( clkNum == 16 ) - - //multiCLK 需要按照滞后相位接线，即0为最先到达，1次先 - val multiCLK = IO(Input(Vec(clkNum, Bool()))) - - - val sampleReg = Wire(Vec(clkNum, Bool())) - dontTouch(sampleReg) - - for( i <- 0 until clkNum ) { - sampleReg(i) := withClockAndReset(multiCLK(i).asClock, reset.asBool){ ShiftRegister( io.serDat, 2, false.B, true.B ) } - } - - val sampleReg_sync = for( i <- 0 until clkNum ) yield { - ShiftRegisters(sampleReg(i), 8) - } - for( i <- 0 until clkNum; j <- 0 until 8 ){dontTouch(sampleReg_sync(i)(j))} - - val sampleReg_Align = Wire(Vec(8*clkNum,Bool())) - dontTouch(sampleReg_Align) - - - for( i <- 0 until clkNum ){ - sampleReg_Align(i) := sampleReg_sync(i)(7) - } - - for( i <- clkNum until 2*clkNum ){ - sampleReg_Align(i) := sampleReg_sync(i-clkNum)(6) - } - - for( i <- 2*clkNum until 3*clkNum ){ - sampleReg_Align(i) := sampleReg_sync(i-2*clkNum)(5) - } - - for( i <- 3*clkNum until 4*clkNum ){ - sampleReg_Align(i) := sampleReg_sync(i-3*clkNum)(4) - } - - for( i <- 4*clkNum until 5*clkNum ){ - sampleReg_Align(i) := sampleReg_sync(i-4*clkNum)(3) - } - - for( i <- 5*clkNum until 6*clkNum ){ - sampleReg_Align(i) := sampleReg_sync(i-5*clkNum)(2) - } - - for( i <- 6*clkNum until 7*clkNum ){ - sampleReg_Align(i) := sampleReg_sync(i-6*clkNum)(1) - } - - for( i <- 7*clkNum until 8*clkNum ){ - sampleReg_Align(i) := sampleReg_sync(i-7*clkNum)(0) - } - - - - - val flitReg = - for( i <- 1 until (8*clkNum)-1 ) yield { - (sampleReg_Align(i-1) & sampleReg_Align(i+0)) | - (sampleReg_Align(i-1) & sampleReg_Align(i+1)) | - (sampleReg_Align(i+0) & sampleReg_Align(i+1)) - } - for( i <- 0 until (8*clkNum)-2 ) {dontTouch(flitReg(i))} - - val clearCnt = RegInit(0.U(4.W)) - val checkCnt = RegInit(0.U(4.W)) - val arbCali = RegInit(0.U( (log2Ceil(8*clkNum)).W )) - val isLock = RegInit(false.B) - - when( (7*clkNum until 8*clkNum).map{ i => sampleReg_Align(i)}.reduce(_|_) === false.B ){ - when( clearCnt =/= 10.U ){ - clearCnt := clearCnt + 1.U - } - } .otherwise{ - clearCnt := 0.U - } - - when( ~isLock ){ - checkCnt := 0.U - } .otherwise{ - checkCnt := checkCnt + 1.U - } - - //优先级电路，优先选择跳变的后一相进行操作，电路上需要做成可调的 - val checkWindow = Wire( Vec(6, Bool()) ) - dontTouch(checkWindow) - - checkWindow(0) := - Mux1H( (0 until 116).map{ i => - (arbCali === (i+2).U) -> flitReg(i) - }) - - checkWindow(1) := - Mux1H( (1 until 117).map{ i => - (arbCali === (i+1).U) -> flitReg(i) - }) - - checkWindow(2) := - Mux1H( (2 until 118).map{ i => - (arbCali === i.U) -> flitReg(i) - }) - - checkWindow(3) := - Mux1H( (3 until 119).map{ i => - (arbCali === (i-1).U) -> flitReg(i) - }) - - checkWindow(4) := - Mux1H( (4 until 120).map{ i => - (arbCali === (i-2).U) -> flitReg(i) - }) - - checkWindow(5) := - Mux1H( (5 until 121).map{ i => - (arbCali === (i-3).U) -> flitReg(i) - }) - - when( ~isLock ){ - for( i <- 0 until 16 ){ - val j = 50+16 - i - 1 - when( flitReg(j) ^ flitReg(j+1) ){ - arbCali := j.U - } - } - }.elsewhen( checkCnt.andR ){ //锁定之后，只允许每16cycle移动一相位 - assert( arbCali >= 2.U && arbCali < 118.U ) - - when( - (checkWindow(0) ^ checkWindow(1)) | - (checkWindow(1) ^ checkWindow(2)) - ){ - when( arbCali =/= 2.U ){ - arbCali := arbCali - 1.U - } - } .elsewhen( - (checkWindow(3) ^ checkWindow(4)) | - (checkWindow(4) ^ checkWindow(5)) - ){ - when( arbCali =/= 117.U ){ - arbCali := arbCali + 1.U - } - } - } - - when( ~isLock ){ - for( i <- 0 until 16 ){ - val j = 50+16 - i - 1 - when( flitReg(j) ^ flitReg(j+1) ){ - isLock := true.B - } - } - } .elsewhen( clearCnt === 10.U ){ - isLock := false.B - } - - - val asyncSerDat = - Mux1H( - (for { i <- 2 until 118 } yield { - (arbCali === i.U) -> flitReg(i+(8)) - }) - ) - - - io.syncSerDat := asyncSerDat - -} - -class CDRInAxisIO extends Bundle{ - val axis = Decoupled(new AXIS_Bundle(8)) - val decode = Flipped(new Decode_Bundle) - val syncSerDat = Input(Bool()) - - val flush = Input(Bool()) -} - -class CDRInAxis extends Module with RequireAsyncReset{ - val io: CDRInAxisIO = IO(new CDRInAxisIO) - - io.decode.dataIn := 0.U - def HeaderByte: Int = 4 - - val ETH_PRE = "h68".U(8.W) - val ETH_SFD = "h25".U(8.W) - - val STATE_IDLE = 0.U - val STATE_HEADER = 1.U - val STATE_PAYLOAD = 2.U - - val stateNext = Wire(UInt(2.W)) - val stateCurr = RegNext( stateNext, STATE_IDLE ) - - val bitCnt = RegInit(0.U(4.W)) - val byteCnt = RegInit(0.U((12+1).W)) - - val checkSFD = RegInit( 0.U(10.W) ) - - when( io.flush ){ - checkSFD := 0.U - } .otherwise{ - checkSFD := Cat( checkSFD(8,0), io.syncSerDat ) - } - - io.decode.dataIn := checkSFD(9,0) - val shiftData = io.decode.dataOut - val shiftData10Next = ShiftRegister( shiftData, 10, 0.U(8.W), true.B ) - - val payloadLen = RegInit(0.U(12.W)) - - when( io.flush ){ - payloadLen := 0.U - } .elsewhen( byteCnt === 0.U & bitCnt === 9.U & stateCurr === STATE_HEADER ){ - payloadLen := Cat( shiftData, 0.U(4.W) ) - } .elsewhen( byteCnt === 1.U & bitCnt === 9.U & stateCurr === STATE_HEADER ){ - payloadLen := Cat( payloadLen(11,4), shiftData(7,4) ) - } - - stateNext := - Mux( io.flush, STATE_IDLE, - Mux1H(Seq( - (stateCurr === STATE_IDLE) -> ( Mux( shiftData10Next === ETH_PRE && shiftData === ETH_SFD , STATE_HEADER, STATE_IDLE )), //IDLE - (stateCurr === STATE_HEADER) -> ( Mux( (byteCnt === (HeaderByte-1).U) & (bitCnt === 9.U), STATE_PAYLOAD, STATE_HEADER ) ), - (stateCurr === STATE_PAYLOAD) -> ( Mux( (byteCnt === (payloadLen + (4 - 1).U) ) & (bitCnt === 9.U), STATE_IDLE, STATE_PAYLOAD )), // PAYLOAD - )) //crc - ) - - - - - - when( stateCurr === STATE_IDLE & ( shiftData10Next === ETH_PRE && shiftData === ETH_SFD ) ){ //first align - bitCnt := 0.U - } .otherwise{ - when( bitCnt === 9.U ){ - bitCnt := 0.U - } .otherwise{ - bitCnt := bitCnt + 1.U - } - } - - when( io.flush ){ - byteCnt := 0.U - } .elsewhen( stateCurr === STATE_IDLE & ( shiftData10Next === ETH_PRE && shiftData === ETH_SFD ) ){ //first align - byteCnt := 0.U - } .elsewhen( bitCnt === 9.U ){ - when( stateCurr === STATE_HEADER ){ - byteCnt := Mux( byteCnt =/= (HeaderByte-1).U, byteCnt + 1.U, 0.U ) - assert( byteCnt <= (HeaderByte-1).U ) - } .elsewhen( stateCurr === STATE_PAYLOAD ){ - byteCnt := Mux( byteCnt =/= (payloadLen+ (4-1).U), byteCnt + 1.U, 0.U ) - assert( byteCnt <= ( payloadLen+ (4-1).U ) ) - } - } - - - - - - val axis_valid = RegInit(false.B) - val axis_tdata = RegEnable( shiftData, 0.U(8.W), bitCnt === 9.U & ( stateCurr === STATE_HEADER | stateCurr === STATE_PAYLOAD ) ) - val axis_tuser = false.B - val axis_tlast = RegInit( false.B ) - - - - io.axis.valid := axis_valid - io.axis.bits.tdata := axis_tdata - io.axis.bits.tuser := axis_tuser - io.axis.bits.tlast := axis_tlast - - when( io.flush ){ - axis_valid := false.B - } .elsewhen( io.axis.fire ){ - axis_valid := false.B - } .elsewhen( bitCnt === 9.U & ( stateCurr === STATE_HEADER | stateCurr === STATE_PAYLOAD ) ){ - axis_valid := true.B - } - - when( io.flush ){ - axis_tlast := false.B - } .otherwise{ - axis_tlast := (stateCurr === STATE_PAYLOAD & stateNext === STATE_IDLE) - } - -} - - - +package BACK + +import chisel3._ +import chisel3.util._ + + + +class CDRInSampleIO extends Bundle{ + val serDat = Input(Bool()) + val syncSerDat = Output(Bool()) +} + + +class CDRInMultiSample extends Module with RequireAsyncReset{ + val io: CDRInSampleIO = IO(new CDRInSampleIO) + val clkNum: Int = 16 + require( clkNum == 16 ) + + //multiCLK 需要按照滞后相位接线，即0为最先到达，1次先 + val multiCLK = IO(Input(Vec(clkNum, Bool()))) + + + val sampleReg = Wire(Vec(clkNum, Bool())) + dontTouch(sampleReg) + + for( i <- 0 until clkNum ) { + sampleReg(i) := withClockAndReset(multiCLK(i).asClock, reset.asBool){ ShiftRegister( io.serDat, 2, false.B, true.B ) } + } + + val sampleReg_sync = for( i <- 0 until clkNum ) yield { + ShiftRegisters(sampleReg(i), 8) + } + for( i <- 0 until clkNum; j <- 0 until 8 ){dontTouch(sampleReg_sync(i)(j))} + + val sampleReg_Align = Wire(Vec(8*clkNum,Bool())) + dontTouch(sampleReg_Align) + + + for( i <- 0 until clkNum ){ + sampleReg_Align(i) := sampleReg_sync(i)(7) + } + + for( i <- clkNum until 2*clkNum ){ + sampleReg_Align(i) := sampleReg_sync(i-clkNum)(6) + } + + for( i <- 2*clkNum until 3*clkNum ){ + sampleReg_Align(i) := sampleReg_sync(i-2*clkNum)(5) + } + + for( i <- 3*clkNum until 4*clkNum ){ + sampleReg_Align(i) := sampleReg_sync(i-3*clkNum)(4) + } + + for( i <- 4*clkNum until 5*clkNum ){ + sampleReg_Align(i) := sampleReg_sync(i-4*clkNum)(3) + } + + for( i <- 5*clkNum until 6*clkNum ){ + sampleReg_Align(i) := sampleReg_sync(i-5*clkNum)(2) + } + + for( i <- 6*clkNum until 7*clkNum ){ + sampleReg_Align(i) := sampleReg_sync(i-6*clkNum)(1) + } + + for( i <- 7*clkNum until 8*clkNum ){ + sampleReg_Align(i) := sampleReg_sync(i-7*clkNum)(0) + } + + + + + val flitReg = + for( i <- 1 until (8*clkNum)-1 ) yield { + (sampleReg_Align(i-1) & sampleReg_Align(i+0)) | + (sampleReg_Align(i-1) & sampleReg_Align(i+1)) | + (sampleReg_Align(i+0) & sampleReg_Align(i+1)) + } + for( i <- 0 until (8*clkNum)-2 ) {dontTouch(flitReg(i))} + + val clearCnt = RegInit(0.U(4.W)) + val checkCnt = RegInit(0.U(4.W)) + val arbCali = RegInit(0.U( (log2Ceil(8*clkNum)).W )) + val isLock = RegInit(false.B) + + when( (7*clkNum until 8*clkNum).map{ i => sampleReg_Align(i)}.reduce(_|_) === false.B ){ + when( clearCnt =/= 10.U ){ + clearCnt := clearCnt + 1.U + } + } .otherwise{ + clearCnt := 0.U + } + + when( ~isLock ){ + checkCnt := 0.U + } .otherwise{ + checkCnt := checkCnt + 1.U + } + + //优先级电路，优先选择跳变的后一相进行操作，电路上需要做成可调的 + val checkWindow = Wire( Vec(6, Bool()) ) + dontTouch(checkWindow) + + checkWindow(0) := + Mux1H( (0 until 116).map{ i => + (arbCali === (i+2).U) -> flitReg(i) + }) + + checkWindow(1) := + Mux1H( (1 until 117).map{ i => + (arbCali === (i+1).U) -> flitReg(i) + }) + + checkWindow(2) := + Mux1H( (2 until 118).map{ i => + (arbCali === i.U) -> flitReg(i) + }) + + checkWindow(3) := + Mux1H( (3 until 119).map{ i => + (arbCali === (i-1).U) -> flitReg(i) + }) + + checkWindow(4) := + Mux1H( (4 until 120).map{ i => + (arbCali === (i-2).U) -> flitReg(i) + }) + + checkWindow(5) := + Mux1H( (5 until 121).map{ i => + (arbCali === (i-3).U) -> flitReg(i) + }) + + when( ~isLock ){ + for( i <- 0 until 16 ){ + val j = 50+16 - i - 1 + when( flitReg(j) ^ flitReg(j+1) ){ + arbCali := j.U + } + } + }.elsewhen( checkCnt.andR ){ //锁定之后，只允许每16cycle移动一相位 + assert( arbCali >= 2.U && arbCali < 118.U ) + + when( + (checkWindow(0) ^ checkWindow(1)) | + (checkWindow(1) ^ checkWindow(2)) + ){ + when( arbCali =/= 2.U ){ + arbCali := arbCali - 1.U + } + } .elsewhen( + (checkWindow(3) ^ checkWindow(4)) | + (checkWindow(4) ^ checkWindow(5)) + ){ + when( arbCali =/= 117.U ){ + arbCali := arbCali + 1.U + } + } + } + + when( ~isLock ){ + for( i <- 0 until 16 ){ + val j = 50+16 - i - 1 + when( flitReg(j) ^ flitReg(j+1) ){ + isLock := true.B + } + } + } .elsewhen( clearCnt === 10.U ){ + isLock := false.B + } + + + val asyncSerDat = + Mux1H( + (for { i <- 2 until 118 } yield { + (arbCali === i.U) -> flitReg(i+(8)) + }) + ) + + + io.syncSerDat := asyncSerDat + +} + +class CDRInAxisIO extends Bundle{ + val axis = Decoupled(new AXIS_Bundle(8)) + val decode = Flipped(new Decode_Bundle) + val syncSerDat = Input(Bool()) + + val flush = Input(Bool()) +} + +class CDRInAxis extends Module with RequireAsyncReset{ + val io: CDRInAxisIO = IO(new CDRInAxisIO) + + io.decode.dataIn := 0.U + def HeaderByte: Int = 4 + + val ETH_PRE = "h68".U(8.W) + val ETH_SFD = "h25".U(8.W) + + val STATE_IDLE = 0.U + val STATE_HEADER = 1.U + val STATE_PAYLOAD = 2.U + + val stateNext = Wire(UInt(2.W)) + val stateCurr = RegNext( stateNext, STATE_IDLE ) + + val bitCnt = RegInit(0.U(4.W)) + val byteCnt = RegInit(0.U((12+1).W)) + + val checkSFD = RegInit( 0.U(10.W) ) + + when( io.flush ){ + checkSFD := 0.U + } .otherwise{ + checkSFD := Cat( checkSFD(8,0), io.syncSerDat ) + } + + io.decode.dataIn := checkSFD(9,0) + val shiftData = io.decode.dataOut + val shiftData10Next = ShiftRegister( shiftData, 10, 0.U(8.W), true.B ) + + val payloadLen = RegInit(0.U(12.W)) + + when( io.flush ){ + payloadLen := 0.U + } .elsewhen( byteCnt === 0.U & bitCnt === 9.U & stateCurr === STATE_HEADER ){ + payloadLen := Cat( shiftData, 0.U(4.W) ) + } .elsewhen( byteCnt === 1.U & bitCnt === 9.U & stateCurr === STATE_HEADER ){ + payloadLen := Cat( payloadLen(11,4), shiftData(7,4) ) + } + + stateNext := + Mux( io.flush, STATE_IDLE, + Mux1H(Seq( + (stateCurr === STATE_IDLE) -> ( Mux( shiftData10Next === ETH_PRE && shiftData === ETH_SFD , STATE_HEADER, STATE_IDLE )), //IDLE + (stateCurr === STATE_HEADER) -> ( Mux( (byteCnt === (HeaderByte-1).U) & (bitCnt === 9.U), STATE_PAYLOAD, STATE_HEADER ) ), + (stateCurr === STATE_PAYLOAD) -> ( Mux( (byteCnt === (payloadLen + (4 - 1).U) ) & (bitCnt === 9.U), STATE_IDLE, STATE_PAYLOAD )), // PAYLOAD + )) //crc + ) + + + + + + when( stateCurr === STATE_IDLE & ( shiftData10Next === ETH_PRE && shiftData === ETH_SFD ) ){ //first align + bitCnt := 0.U + } .otherwise{ + when( bitCnt === 9.U ){ + bitCnt := 0.U + } .otherwise{ + bitCnt := bitCnt + 1.U + } + } + + when( io.flush ){ + byteCnt := 0.U + } .elsewhen( stateCurr === STATE_IDLE & ( shiftData10Next === ETH_PRE && shiftData === ETH_SFD ) ){ //first align + byteCnt := 0.U + } .elsewhen( bitCnt === 9.U ){ + when( stateCurr === STATE_HEADER ){ + byteCnt := Mux( byteCnt =/= (HeaderByte-1).U, byteCnt + 1.U, 0.U ) + assert( byteCnt <= (HeaderByte-1).U ) + } .elsewhen( stateCurr === STATE_PAYLOAD ){ + byteCnt := Mux( byteCnt =/= (payloadLen+ (4-1).U), byteCnt + 1.U, 0.U ) + assert( byteCnt <= ( payloadLen+ (4-1).U ) ) + } + } + + + + + + val axis_valid = RegInit(false.B) + val axis_tdata = RegEnable( shiftData, 0.U(8.W), bitCnt === 9.U & ( stateCurr === STATE_HEADER | stateCurr === STATE_PAYLOAD ) ) + val axis_tuser = false.B + val axis_tlast = RegInit( false.B ) + + + + io.axis.valid := axis_valid + io.axis.bits.tdata := axis_tdata + io.axis.bits.tuser := axis_tuser + io.axis.bits.tlast := axis_tlast + + when( io.flush ){ + axis_valid := false.B + } .elsewhen( io.axis.fire ){ + axis_valid := false.B + } .elsewhen( bitCnt === 9.U & ( stateCurr === STATE_HEADER | stateCurr === STATE_PAYLOAD ) ){ + axis_valid := true.B + } + + when( io.flush ){ + axis_tlast := false.B + } .otherwise{ + axis_tlast := (stateCurr === STATE_PAYLOAD & stateNext === STATE_IDLE) + } + +} + + + diff --git a/src/main/scala/backBoard/ebus/CDROut.scala b/src/main/scala/backBoard/shin/CDROut.scala similarity index 96% rename from src/main/scala/backBoard/ebus/CDROut.scala rename to src/main/scala/backBoard/shin/CDROut.scala index 6fd4ccd..afdf05a 100644 --- a/src/main/scala/backBoard/ebus/CDROut.scala +++ b/src/main/scala/backBoard/shin/CDROut.scala @@ -1,117 +1,117 @@ -package BACK - -import chisel3._ -import chisel3.util._ - -class AXIS_Bundle(dw: Int) extends Bundle{ - val tdata = UInt(dw.W) - val tlast = Bool() - val tuser = Bool() -} - - - - -//work in 100MHZ -class CDROutIO extends Bundle{ - val axis = Flipped(Decoupled(new AXIS_Bundle(8))) - val encode = Flipped(new Encode_Bundle) - val serDat = Output(Bool()) - - - val flush = Input(Bool()) - - - -} - - -class CDROut extends Module with RequireAsyncReset{ - val io: CDROutIO = IO(new CDROutIO) - def PRE_NUM = 3 //PRE_NUM should >= 3 - - - def STATE_IDLE = 0.U - def STATE_PREAMBLE = 1.U - def STATE_PAYLOAD = 2.U - - val ETH_PRE = "h68".U(8.W) - val ETH_SFD = "h25".U(8.W) - - val stateNext = Wire(UInt(2.W)) - val stateCurr = RegNext( stateNext, 0.U ) - - - val bitCnt = RegInit(0.U(4.W)) - val byteCnt = RegInit(0.U(3.W)) //payload dont need to count - - val shiftData = RegInit(0.U(10.W)) - io.encode.isEnable := false.B //组合逻辑 - io.encode.dataIn := 0.U //组合逻辑 - - stateNext := - Mux( io.flush, STATE_IDLE, - Mux1H(Seq( - (stateCurr === STATE_IDLE) -> ( Mux( io.axis.valid, STATE_PREAMBLE, STATE_IDLE )), - (stateCurr === STATE_PREAMBLE) -> ( Mux( (byteCnt === (PRE_NUM-1).U) & (bitCnt === 9.U), Mux( io.axis.valid, STATE_PAYLOAD, STATE_IDLE), STATE_PREAMBLE )), - (stateCurr === STATE_PAYLOAD) -> ( Mux( (io.axis.fire & io.axis.bits.tlast) | (~io.axis.valid & io.axis.ready), STATE_IDLE, STATE_PAYLOAD ) ), - )) - ) - io.serDat := shiftData.extract(9) - io.axis.ready := - bitCnt === 9.U & ( - (stateCurr === STATE_PREAMBLE & byteCnt === (PRE_NUM-1).U) | - (stateCurr === STATE_PAYLOAD) - ) - - // assert( ~(~io.axis.valid & io.axis.ready) ) - when( ~io.axis.valid & io.axis.ready ){ - printf( "Error, CDROut axis overflow!\n" ) - } - - - when( io.flush ){ - shiftData := 0.U - } .elsewhen( stateCurr === STATE_IDLE & stateNext === STATE_PREAMBLE){ //PRE - shiftData := io.encode.dataOut - io.encode.dataIn := ETH_PRE //组合逻辑 - io.encode.isEnable := true.B //组合逻辑 - } .otherwise{ - when( bitCnt =/= 9.U ){ - shiftData := shiftData << 1 - } .otherwise{ //bitCnt === 9.U - when( stateCurr === STATE_PREAMBLE ){ - shiftData := io.encode.dataOut - io.encode.dataIn := MuxCase( ETH_PRE, Array( - ( byteCnt === (PRE_NUM-2).U ) -> ETH_SFD, - ( byteCnt === (PRE_NUM-1).U ) -> io.axis.bits.tdata, - )) //组合逻辑 - io.encode.isEnable := true.B //组合逻辑 - } .elsewhen( stateCurr === STATE_PAYLOAD ){ - io.encode.dataIn := io.axis.bits.tdata //组合逻辑 - shiftData := io.encode.dataOut - io.encode.isEnable := true.B //组合逻辑 - } - } - } - - - when( stateCurr === STATE_IDLE ){ //PRE - bitCnt := 0.U - } .otherwise{ - when( bitCnt === 9.U ){ - bitCnt := 0.U - } .otherwise{ - bitCnt := bitCnt + 1.U - } - } - - when( (stateCurr === STATE_IDLE) | (stateCurr === STATE_PAYLOAD) ){ - byteCnt := 0.U - } .elsewhen( bitCnt === 9.U ){ - byteCnt := byteCnt + 1.U - } - - -} - +package BACK + +import chisel3._ +import chisel3.util._ + +class AXIS_Bundle(dw: Int) extends Bundle{ + val tdata = UInt(dw.W) + val tlast = Bool() + val tuser = Bool() +} + + + + +//work in 100MHZ +class CDROutIO extends Bundle{ + val axis = Flipped(Decoupled(new AXIS_Bundle(8))) + val encode = Flipped(new Encode_Bundle) + val serDat = Output(Bool()) + + + val flush = Input(Bool()) + + + +} + + +class CDROut extends Module with RequireAsyncReset{ + val io: CDROutIO = IO(new CDROutIO) + def PRE_NUM = 3 //PRE_NUM should >= 3 + + + def STATE_IDLE = 0.U + def STATE_PREAMBLE = 1.U + def STATE_PAYLOAD = 2.U + + val ETH_PRE = "h68".U(8.W) + val ETH_SFD = "h25".U(8.W) + + val stateNext = Wire(UInt(2.W)) + val stateCurr = RegNext( stateNext, 0.U ) + + + val bitCnt = RegInit(0.U(4.W)) + val byteCnt = RegInit(0.U(3.W)) //payload dont need to count + + val shiftData = RegInit(0.U(10.W)) + io.encode.isEnable := false.B //组合逻辑 + io.encode.dataIn := 0.U //组合逻辑 + + stateNext := + Mux( io.flush, STATE_IDLE, + Mux1H(Seq( + (stateCurr === STATE_IDLE) -> ( Mux( io.axis.valid, STATE_PREAMBLE, STATE_IDLE )), + (stateCurr === STATE_PREAMBLE) -> ( Mux( (byteCnt === (PRE_NUM-1).U) & (bitCnt === 9.U), Mux( io.axis.valid, STATE_PAYLOAD, STATE_IDLE), STATE_PREAMBLE )), + (stateCurr === STATE_PAYLOAD) -> ( Mux( (io.axis.fire & io.axis.bits.tlast) | (~io.axis.valid & io.axis.ready), STATE_IDLE, STATE_PAYLOAD ) ), + )) + ) + io.serDat := shiftData.extract(9) + io.axis.ready := + bitCnt === 9.U & ( + (stateCurr === STATE_PREAMBLE & byteCnt === (PRE_NUM-1).U) | + (stateCurr === STATE_PAYLOAD) + ) + + // assert( ~(~io.axis.valid & io.axis.ready) ) + when( ~io.axis.valid & io.axis.ready ){ + printf( "Error, CDROut axis overflow!\n" ) + } + + + when( io.flush ){ + shiftData := 0.U + } .elsewhen( stateCurr === STATE_IDLE & stateNext === STATE_PREAMBLE){ //PRE + shiftData := io.encode.dataOut + io.encode.dataIn := ETH_PRE //组合逻辑 + io.encode.isEnable := true.B //组合逻辑 + } .otherwise{ + when( bitCnt =/= 9.U ){ + shiftData := shiftData << 1 + } .otherwise{ //bitCnt === 9.U + when( stateCurr === STATE_PREAMBLE ){ + shiftData := io.encode.dataOut + io.encode.dataIn := MuxCase( ETH_PRE, Array( + ( byteCnt === (PRE_NUM-2).U ) -> ETH_SFD, + ( byteCnt === (PRE_NUM-1).U ) -> io.axis.bits.tdata, + )) //组合逻辑 + io.encode.isEnable := true.B //组合逻辑 + } .elsewhen( stateCurr === STATE_PAYLOAD ){ + io.encode.dataIn := io.axis.bits.tdata //组合逻辑 + shiftData := io.encode.dataOut + io.encode.isEnable := true.B //组合逻辑 + } + } + } + + + when( stateCurr === STATE_IDLE ){ //PRE + bitCnt := 0.U + } .otherwise{ + when( bitCnt === 9.U ){ + bitCnt := 0.U + } .otherwise{ + bitCnt := bitCnt + 1.U + } + } + + when( (stateCurr === STATE_IDLE) | (stateCurr === STATE_PAYLOAD) ){ + byteCnt := 0.U + } .elsewhen( bitCnt === 9.U ){ + byteCnt := byteCnt + 1.U + } + + +} + diff --git a/src/main/scala/backBoard/ebus/Encryptor.scala b/src/main/scala/backBoard/shin/Encryptor.scala similarity index 100% rename from src/main/scala/backBoard/ebus/Encryptor.scala rename to src/main/scala/backBoard/shin/Encryptor.scala diff --git a/src/main/scala/backBoard/shin/Interface.scala b/src/main/scala/backBoard/shin/Interface.scala index bd51d81..b3718f0 100644 --- a/src/main/scala/backBoard/shin/Interface.scala +++ b/src/main/scala/backBoard/shin/Interface.scala @@ -255,8 +255,6 @@ abstract class InterfaceBase extends Module with RequireAsyncReset{ (addr === ("h10".U(16.W) + i.U) ) -> cReg.uniCode( 8*i+7,8*i+0 ) }) ++ - - Seq( (addr === "h8".U ) -> cReg.busRate( 7,0 ), (addr === "h9".U ) -> cReg.spiSel, @@ -264,25 +262,14 @@ abstract class InterfaceBase extends Module with RequireAsyncReset{ (addr === "hb".U & isSlvMode) -> sReg.localDevIndex(15,8), ) ++ - Seq( (addr === "h18".U ) -> sReg.lvdsWriteAble.extract(0), (addr === "h20".U & isMstMode) -> Cat(mReg.rxSM, mReg.txSM, 0.U(1.W) ), (addr === "h22".U & isMstMode) -> mReg.isRecCRCErr, - //(addr === "h21".U & isMstMode) -> mReg.txLength, - (addr === "h24".U & isMstMode) -> mReg.rplTimeStampTx(7,0), (addr === "h25".U & isMstMode) -> mReg.rplTimeStampTx(15,8), - - - ) ++ - - - - - Seq( (addr === "h40".U ) -> cReg.softResetCode(1), (addr === "h41".U ) -> cReg.softResetCode(1), @@ -374,14 +361,9 @@ abstract class InterfaceBase extends Module with RequireAsyncReset{ (addr === "hb6".U ) -> cReg.statUpRecByteCnt(55,48), (addr === "hb7".U ) -> cReg.statUpRecByteCnt(63,56), - - - (addr === "hc0".U ) -> Cat( sReg.isDevOnRightModify, sReg.isDevOnRight, 0.U(3.W) ), (addr === "hc2".U ) -> sReg.indexOfRightDev(7,0), (addr === "hc3".U ) -> sReg.indexOfRightDev(13,8), - // (addr === "hc4".U ) -> sReg.indexOfLeftDev(7,0), - // (addr === "hc5".U ) -> sReg.indexOfLeftDev(13,8), ) ++ Seq( @@ -500,18 +482,12 @@ abstract class InterfaceBase extends Module with RequireAsyncReset{ )}.reduce(_++_) ++ ( 0 until 8 ).map{ i => ( addr === ("h301".U(16.W) + (i*4).U) ) -> cReg.smUsedDepth(i) - } ++ - ( 0 until 8 ).map{ i => ( addr === ("h302".U(16.W) + (i*4).U) ) -> cReg.smTrigLen(i)(7,0) - } ++ - ( 0 until 8 ).map{ i => ( addr === ("h303".U(16.W) + (i*4).U) ) -> cReg.smTrigLen(i)(10,8) } ++ ( 0 until 4 ).map{ i => ( addr === ("h400".U(16.W) + i.U) ) -> cReg.wdtStatus( 8*i+7, 8*i+0 ) - } ++ - ( 0 until 4 ).map{ i => ( addr === ("h404".U(16.W) + i.U) ) -> cReg.wdtEnable( 8*i+7, 8*i+0 ) } ++ (for( i <- 0 until 17; j <- 0 until 4 ) yield { @@ -525,26 +501,12 @@ abstract class InterfaceBase extends Module with RequireAsyncReset{ ) ++ ( 0 until 8 ).map{ i => ( addr === ("h508".U(16.W) + i.U) ) -> cReg.event.posedgeTimeStampLatch(0)( 8*i+7, 8*i+0 ) - } ++ - ( 0 until 8 ).map{ i => ( addr === ("h510".U(16.W) + i.U) ) -> cReg.event.negedgeTimeStampLatch(0)( 8*i+7, 8*i+0 ) - } ++ - ( 0 until 8 ).map{ i => ( addr === ("h518".U(16.W) + i.U) ) -> cReg.event.posedgeTimeStampLatch(1)( 8*i+7, 8*i+0 ) - } ++ - ( 0 until 8 ).map{ i => ( addr === ("h520".U(16.W) + i.U) ) -> cReg.event.negedgeTimeStampLatch(1)( 8*i+7, 8*i+0 ) - } ++ - ( 0 until 8 ).map{ i => ( addr === ("h528".U(16.W) + i.U) ) -> cReg.event.mcuSMTimeStampEnq( 8*i+7, 8*i+0 ) - } ++ - ( 0 until 8 ).map{ i => ( addr === ("h530".U(16.W) + i.U) ) -> cReg.event.mcuSMTimeStampDeq( 8*i+7, 8*i+0 ) - } ++ - ( 0 until 8 ).map{ i => ( addr === ("h538".U(16.W) + i.U) ) -> cReg.event.lvdsSMTimeStampEnq( 8*i+7, 8*i+0 ) - } ++ - ( 0 until 8 ).map{ i => ( addr === ("h540".U(16.W) + i.U) ) -> cReg.event.lvdsSMTimeStampDeq( 8*i+7, 8*i+0 ) } ++ Seq() @@ -569,12 +531,6 @@ abstract class InterfaceBase extends Module with RequireAsyncReset{ trait InterfaceMCUop{ this: InterfaceBase => - - - - - - isEnW := Mux1H(Seq( ( cReg.spiSel === 0.U ) -> iQSpi.io.isEnW, ( cReg.spiSel === 1.U ) -> oSpi.io.isEnW, @@ -638,7 +594,6 @@ trait InterfaceMCUop{ this: InterfaceBase => mReg.txSM := RegEnable( dataw(2,1), 0.U(2.W), isEnW & addrw === "h20".U ) mReg.rxSM := RegEnable( dataw(4,3), 0.U(2.W), isEnW & addrw === "h20".U ) - // mReg.txLength := Cat( RegEnable( dataw, 0.U, isEnW & addrw === "h22".U ), RegEnable( dataw, 0.U, isEnW & addrw === "h21".U ) ) val mReg_isRecCRCErr = RegInit(0.U(4.W)) mReg.isRecCRCErr := mReg_isRecCRCErr @@ -680,7 +635,6 @@ trait InterfaceCheckSM{ this: InterfaceBase => for( i <- 0 until 8 ){ - io.isSMReset(i) := isEnW & (addrw === ("h300".U(16.W) + (i*4).U)) cReg.smUsedDepth(i) := io.smUsedDepth(i) @@ -699,10 +653,6 @@ trait InterfaceCheckSM{ this: InterfaceBase => smTrigLen_L(i) := io.lvds.dataw } } - - - - } @@ -746,8 +696,6 @@ trait InterfaceEBMMU{ this: InterfaceBase => io.lvds.datar := RegEnable(AcquireReg(addr = io.lvds.addrr), 0.U(8.W), io.lvds.isEnR) - - ( 0 until 16 ).map{ i => sReg.ebmmu(i).lAddr := Cat( RegEnable( io.lvds.dataw(5,0), 0.U(8.W), sReg.isLVDSWriteAble & io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h203".U(16.W) + (10*i).U )) ), @@ -1040,8 +988,8 @@ trait InterfaceWdt{ this: InterfaceBase => cReg.wdtEnable := Cat( RegEnable( dataw(1,0), 0.U(2.W), isEnW & addrw === "h406".U ), - RegEnable( dataw, 0.U(8.W), isEnW & addrw === "h405".U ), - RegEnable( dataw, 0.U(8.W), isEnW & addrw === "h404".U ), + RegEnable( dataw, 0.U(8.W), isEnW & addrw === "h405".U ), + RegEnable( dataw, 0.U(8.W), isEnW & addrw === "h404".U ), ) for( i <- 0 until 18 ){ @@ -1145,9 +1093,6 @@ trait InterfaceInterrupt{ this: InterfaceBase => intStatus(4) := true.B } - - - //从站SM请求 for( i <- 0 until 8 ){ when( io.intSlvTrig(i) ){ @@ -1398,11 +1343,6 @@ trait InterfaceStat{ this: InterfaceBase => statDownRecByteCnt := statDownRecByteCnt + 1.U } - - - - - when(io.lvds.isEnW & (io.lvds.addrw === "ha0".U )){ statUpRecErrorCnt := 0.U } .elsewhen( io.upRecStat.isRecError ){ @@ -1475,10 +1415,7 @@ with InterfaceAnalog io.txReq.bits.txSM := mReg.txSM io.txReq.bits.rxSM := mReg.rxSM - // io.txReq.bits.txLength := //mReg.txLength - io.txReq.valid := RegNext(isEnW & addrw === "h20".U & dataw.extract(0) === "b1".U, false.B) //& mReg.txLength =/= 0.U - - + io.txReq.valid := RegNext(isEnW & addrw === "h20".U & dataw.extract(0) === "b1".U, false.B) sReg.localDevIndex := io.localDevIndex @@ -1487,6 +1424,5 @@ with InterfaceAnalog sReg.isDevOnRightModify := io.isDevOnRightModify sReg.indexOfRightDev := io.indexOfRightDev +} - -} \ No newline at end of file diff --git a/src/main/scala/backBoard/shin/MasterParser.scala b/src/main/scala/backBoard/shin/MasterParser.scala index 6bde127..9ce1cb6 100644 --- a/src/main/scala/backBoard/shin/MasterParser.scala +++ b/src/main/scala/backBoard/shin/MasterParser.scala @@ -43,11 +43,6 @@ abstract class MasterParserBase extends Module with RequireAsyncReset{ val txcrc = Module(new crc32_8) val rxcrc = Module(new crc32_8) - - - - // io.req.ready := reqReady - when( io.req ){ reqReady := false.B } .elsewhen( io.downOut.fire & txCnt === txLen + (4-1).U ){ @@ -134,8 +129,6 @@ abstract class MasterParserBase extends Module with RequireAsyncReset{ io.downOut.bits.tuser := false.B io.downOut.bits.tlast := txCnt === (txLen + 3.U) - - val recCrcCheck = RegInit(0.U(32.W)) when( io.req ){ @@ -154,16 +147,10 @@ abstract class MasterParserBase extends Module with RequireAsyncReset{ io.rsp.valid := io.upIn.fire & io.upIn.bits.tlast io.rsp.bits.isError := io.upIn.fire & io.upIn.bits.tlast & (Cat( recCrcCheck(31,8), io.upIn.bits.tdata ) =/= rxcrc.io.crc) - // io.rsp.bits.length := rxCnt + 1.U - - io.rxEnq := io.upIn.fire & io.upIn.bits.tlast io.txDeq := io.downOut.fire & io.downOut.bits.tlast - - - txcrc.io.isEnable := io.downOut.fire & txCnt < txLen txcrc.io.dataIn := io.downOut.bits.tdata txcrc.io.flush := reqReady @@ -172,8 +159,6 @@ abstract class MasterParserBase extends Module with RequireAsyncReset{ rxcrc.io.dataIn := io.upIn.bits.tdata rxcrc.io.flush := io.rsp.fire - - when( io.upIn.fire ){ when( rxCnt === rxLen ){ recCrcCheck := io.upIn.bits.tdata << 24 @@ -199,7 +184,6 @@ trait MasterParserStat{ this: MasterParserBase => io.upRecStat.isFinish := io.rsp.valid & ~io.rsp.bits.isError io.upRecStat.isRecByteAck := io.upIn.fire - } class MasterParser extends MasterParserBase diff --git a/src/main/scala/backBoard/shin/MstSlvSwitch.scala b/src/main/scala/backBoard/shin/MstSlvSwitch.scala index e79da61..a3aabf1 100644 --- a/src/main/scala/backBoard/shin/MstSlvSwitch.scala +++ b/src/main/scala/backBoard/shin/MstSlvSwitch.scala @@ -352,9 +352,6 @@ trait MstSlvSwitchMaster{ this: MstSlvSwitchBase => } masterParser.io.req := interface.io.txReq.valid - // masterParser.io.req.bits.txLength := interface.io.txReq.bits.txLength - - // io.rsp := masterParser.io.rsp masterParser.io.cReg := interface.io.cReg masterParser.io.mReg := interface.io.mReg @@ -440,9 +437,6 @@ trait MstSlvSwitchSlave{ this: MstSlvSwitchBase => interface.io.localDevIndex := slaveParser.io.localDevIndex //从站链路寄存器 - // interface.io.isDevOnLeft := slaveParser.io.isDevOnLeft - // interface.io.isDevOnLeftModify := slaveParser.io.isDevOnLeftModify - // interface.io.indexOfLeftDev := slaveParser.io.indexOfLeftDev interface.io.isDevOnRight := slaveParser.io.isDevOnRight interface.io.isDevOnRightModify := slaveParser.io.isDevOnRightModify interface.io.indexOfRightDev := slaveParser.io.indexOfRightDev @@ -627,12 +621,6 @@ trait MstSlvSwitchCDRIn{ this: MstSlvSwitchBase => val cdrSelC = interface.io.cReg.cdrParam === 2.U val cdrSelA = ~cdrSelB & ~cdrSelC - // val downCDRSampleIn = Vec(3, Flipped(new CDRInSampleIO) ) - // val upCDRSampleIn = Vec(3, Flipped(new CDRInSampleIO) ) - - - - when(cdrSelB){ io.downCDRSampleIn(1).serDat := downInSerDat io.upCDRSampleIn(1).serDat := upInSerDat diff --git a/src/main/scala/backBoard/shin/NSpiInterface.scala.bk b/src/main/scala/backBoard/shin/NSpiInterface.scala.bk deleted file mode 100644 index 207d97b..0000000 --- a/src/main/scala/backBoard/shin/NSpiInterface.scala.bk +++ /dev/null @@ -1,147 +0,0 @@ -package BACK - -import chisel3._ -import chisel3.util._ - - - -abstract class SyncSpiInterfaceBase extends Module with RequireAsyncReset{ - val io = IO(new RegAccessInterfaceIO) - -} - -class SyncSSpiInterface extends SyncSpiInterfaceBase{ - val spi = IO(new SSPIInterfaceIO) - - // withClockAndReset(sck.asClock, reset.asBool){ - - - - spi.miso := exRego.extract(7) - - val bitSel = withClockAndReset(spi.sck.asClock, spi.csn){RegInit(0.U(3.W)) } - val byteSel = withClockAndReset(spi.sck.asClock, spi.csn){RegInit(0.U(12.W))} - val exRego = withClockAndReset(spi.sck.asClock, spi.csn){RegInit(0.U(8.W))} - val exRegi = withClockAndReset(spi.sck.asClock, spi.csn){RegInit(0.U(8.W))} - - - - when( true.B ){ - bitSel := bitSel + 1.U - } - - when( bitSel.andR ){ - byteSel := byteSel + 1.U - } - - when( true.B ){ - exRegi := Cat( exRegi(6 ,0), spi.mosi ) - } - - - when( bitSel === 0.U ){ - when((byteSel === 1.U || byteSel === 2.U) ){ - exRego := 0.U //地址1，cmd - } .elsewhen( isSpiRead ){ - exRego := datar_async - } - }.otherwise{ - exRego := exRego << 1 - } - - val addrw_async = withClockAndReset(spi.sck.asClock, spi.csn){ RegInit(0.U(16.W)) } - val addrr_async = withClockAndReset(spi.sck.asClock, spi.csn){ RegInit(0.U(16.W)) } - val dataw_async = withClockAndReset(spi.sck.asClock, spi.csn){ RegInit(0.U(8.W)) } - val datar_async = withClockAndReset(spi.sck.asClock, spi.csn){ RegInit(0.U(8.W)) } - val spiCmd = withClockAndReset(spi.sck.asClock, spi.csn){ RegInit(false.B) } - val isSpiWrite = ~spiCmd - val isSpiRead = spiCmd - - when( bitSel === 0.U ){ - when( byteSel === 1.U ){ - addrw_async := exRegi - } .elsewhen( byteSel === 2.U ) { - addrw_async := Cat(addrw_async(7,0), exRegi) - } .elsewhen( byteSel > 3.U ){ - addrw_async := addrw_async + 1.U - } - } - - when( bitSel === 0.U ){ - when( byteSel === 1.U ){ - addrr_async := exRegi - } .elsewhen( byteSel === 2.U ) { - addrr_async := Cat(addrr_async(7,0), exRegi) - } .elsewhen( byteSel > 2.U ){ - addrr_async := addrr_async + 1.U - } - } - - when( byteSel === 2.U & bitSel === 0.U ){ //CS为低，且SCK上跳的第0byte - spiCmd := spi.mosi - } - - - - when( bitSel === 0.U ){ - when( byteSel > 3.U & isSpiWrite ){ - dataw_async := exRegi - } - } - - - - io.dataw := exRegi - io.addrr := Mux( isSpiRead, addrr + 1.U, addrr ) - - // io.addrSel := - // Mux( isSpiRead, addrSel + 1.U, addrSel )//覆盖三种情况 - // val readData = RegEnable(io.datar, io.isEnR) - - - isEnW_async - isEnR_async - addrw_async - addrr_async - datar_async - dataw_async - - - // isEnR_async := bitSel === 1.U & (byteSel >= 2.U) & isSpiRead - // isEnW_async := bitSel === 0.U & (byteSel >= 4.U) & isSpiWrite - - val isEnWSet_async = withClockAndReset(spi.sck.asClock, spi.csn){ RegInit(false.B) } - val isEnWSet_sync = ShiftRegisters(isEnWSet_async, 3, false.B, true.B) - val isEnWReset_async = withClockAndReset(spi.sck.asClock, spi.csn){ ShiftRegister(isEnWSet_sync(1), 2, false.B, true.B) } - - when( bitSel === 0.U & (byteSel >= 4.U) & isSpiWrite ){ - assert( ~isEnWSet_async, "Assert Failed @spi!\n" ) - isEnWSet_async := true.B - } .elsewhen(isEnWReSet_async){ - isEnWSet_async := false.B - } - - io.isEnW := ~isEnWSet_async(2) & isEnWSet_async(1) - io.addrw := addrw_async - io.dataw := dataw_async - - - val isEnRSet_async = withClockAndReset(spi.sck.asClock, spi.csn){ RegInit(false.B) } - val isEnRSet_sync = ShiftRegisters(isEnRSet_async, 3, false.B, true.B) - val isEnRReset_async = withClockAndReset(spi.sck.asClock, spi.csn){ ShiftRegister(isEnRSet_sync(1), 2, false.B, true.B) } - - when( bitSel === 1.U & (byteSel >= 2.U) & isSpiRead ){ - assert( ~isEnRSet_async, "Assert Failed @spi!\n" ) - isEnRSet_async := true.B - } .elsewhen(isEnRReSet_async){ - isEnRSet_async := false.B - } - - io.isEnR := ~isEnRSet_async(2) & isEnRSet_async(1) - io.addrr := addrr_async - datar_async := withClockAndReset(spi.sck.asClock, spi.csn){ RegEnable(io.datar, 0.U, isEnRReSet_async } - - -} - - diff --git a/src/main/scala/backBoard/shin/ShareSRAM.scala b/src/main/scala/backBoard/shin/ShareSRAM.scala index c2819c7..10a4b9b 100644 --- a/src/main/scala/backBoard/shin/ShareSRAM.scala +++ b/src/main/scala/backBoard/shin/ShareSRAM.scala @@ -3,91 +3,6 @@ package BACK import chisel3._ import chisel3.util._ - -class ShareSRAMDP extends BlackBox with HasBlackBoxInline { - - class ShareSRAMDPIO extends Bundle{ - - val addrA = Input(UInt(15.W)) - val datawA = Input( UInt(8.W) ) - val datarA = Output( UInt(8.W) ) - val enwA = Input(Bool()) - val enrA = Input(Bool()) - val clockA = Input(Bool()) - - - val addrB = Input(UInt(15.W)) - val datawB = Input( UInt(8.W) ) - val datarB = Output( UInt(8.W) ) - val enwB = Input(Bool()) - val enrB = Input(Bool()) - val clockB = Input(Bool()) - - } - val io: ShareSRAMDPIO = IO(new ShareSRAMDPIO) - - setInline("ShareSRAMDP.v", - """ - | module ShareSRAMDP( - | input [7:0] datawA, - | input [14:0] addrA, - | input enwA, - | input enrA, - | output [7:0] datarA, - | input clockA, - | - | input [7:0] datawB, - | input [14:0] addrB, - | input enwB, - | input enrB, - | output [7:0] datarB, - | input clockB - | ); - | - | reg [7:0] mem[0:32767]; - | reg [7:0] data_outa_reg = 8'b0; - | reg [7:0] data_outb_reg = 8'b0; - | - | assign datarA = data_outa_reg; - | assign datarB = data_outb_reg; - | - | always@( posedge clockA ) begin - | if( enrA ) begin - | end - | - | if( enwA ) begin - | mem[addrA] <= datawA; - | end else begin - | data_outa_reg <= mem[addrA]; - | end - | end - | - | - | always@( posedge clockB ) begin - | if(enrB) begin - | end - | - | if( enwB ) begin - | mem[addrB] <= datawB; - | end else begin - | data_outb_reg <= mem[addrB]; - | end - | end - | - | initial begin - | for( integer i = 0; i < 32768; i = i + 1 ) begin - | mem[i] = $random; - | end - | end - | - | - |endmodule - """.stripMargin) -} - - - - class ShareSRAM2k extends BlackBox with HasBlackBoxInline { class ShareSRAM2kIO extends Bundle{ diff --git a/src/main/scala/backBoard/shin/SlaveParser.scala b/src/main/scala/backBoard/shin/SlaveParser.scala index d327e68..ff83dba 100644 --- a/src/main/scala/backBoard/shin/SlaveParser.scala +++ b/src/main/scala/backBoard/shin/SlaveParser.scala @@ -26,17 +26,6 @@ class SubMsgTail extends Bundle{ val workCnt = UInt(16.W) //子报文工作计数 } - -// class ShareSRAMIO extends Bundle{ -// val addr = Input(UInt(15.W)) -// val dataw = Input( UInt(8.W) ) -// val datar = Output( UInt(8.W) ) -// val enw = Input(Bool()) -// val enr = Input(Bool()) -// } - - - class SlaveParserIO extends Bundle{ val downIn = Flipped( Decoupled(new AXIS_Bundle(8)) ) val downOut = Decoupled(new AXIS_Bundle(8)) @@ -56,9 +45,6 @@ class SlaveParserIO extends Bundle{ val localDevIndex = Output(UInt(16.W)) //开放链路寄存器组给interface - // val isDevOnLeft = Output(UInt(2.W)) - // val isDevOnLeftModify = Output(Bool()) - // val indexOfLeftDev = Output(UInt(14.W)) val isDevOnRight = Output(UInt(2.W)) val isDevOnRightModify = Output(Bool()) val indexOfRightDev = Output(UInt(14.W)) diff --git a/src/main/scala/backBoard/shin/SlaveRecParser.scala b/src/main/scala/backBoard/shin/SlaveRecParser.scala index ee3eb0b..0707e49 100644 --- a/src/main/scala/backBoard/shin/SlaveRecParser.scala +++ b/src/main/scala/backBoard/shin/SlaveRecParser.scala @@ -65,17 +65,9 @@ class SlaveRecParser extends Module with RequireAsyncReset{ val FRAME_STYLE_COMMON = 0.U val FRAME_STYLE_PROBE = 1.U - - - - - - val lengthCnt = RegInit(0.U(12.W)) //动态计数器 val frameLenCnt = RegInit(0.U(12.W)) //帧长度计数 - - io.frameReq.valid := (stateCurr === STATE_HEADER) & (stateNext === STATE_SUBMSG_HEADER | stateNext === STATE_CRC) val frameHeader = RegInit(0.U.asTypeOf(new FrameHeader)) io.frameReq.bits.frameLenAim := frameHeader.frameLenAim @@ -172,12 +164,6 @@ class SlaveRecParser extends Module with RequireAsyncReset{ } } - - - - - - stateNext := Mux( io.flush, STATE_IDLE, Mux1H(Seq( @@ -212,10 +198,6 @@ class SlaveRecParser extends Module with RequireAsyncReset{ )) ) - - - - io.stat.isHeaderError := stateNext === STATE_ERROR & stateCurr === STATE_HEADER io.stat.isSubHeaderError := stateNext === STATE_ERROR & stateCurr === STATE_SUBMSG_HEADER io.stat.isPayloadError := stateNext === STATE_ERROR & stateCurr === STATE_PAYLOAD_DATA diff --git a/src/main/scala/backBoard/shin/SlaveSendGen.scala b/src/main/scala/backBoard/shin/SlaveSendGen.scala index 9c84bf8..984abe7 100644 --- a/src/main/scala/backBoard/shin/SlaveSendGen.scala +++ b/src/main/scala/backBoard/shin/SlaveSendGen.scala @@ -12,15 +12,12 @@ class SubMsgTxInfo extends SubMsgHeader{ class SlaveSendGenIO extends Bundle{ val data = Vec(2, Flipped( Decoupled(UInt(8.W)) ) ) - - val frameReq = Flipped(Decoupled( new FrameHeader )) val subMsgHeadReq = Flipped(Decoupled( new SubMsgTxInfo )) val subMsgTailReq = Flipped(Decoupled( new SubMsgTail )) val send = Decoupled(new AXIS_Bundle(8)) - val isError = Output(Bool()) val stateCurr = Output(UInt(3.W)) val flush = Input(Bool()) @@ -32,7 +29,6 @@ class SlaveSendGenIO extends Bundle{ class SlaveSendGen extends Module with RequireAsyncReset{ val io: SlaveSendGenIO = IO(new SlaveSendGenIO) - val crc = Module(new crc32_8) val FRAME_STYLE_COMMON = 0.U @@ -50,30 +46,19 @@ class SlaveSendGen extends Module with RequireAsyncReset{ val stateNext = Wire(UInt(3.W)) val stateCurr = RegNext(stateNext, STATE_IDLE); io.stateCurr := stateCurr - io.isError := false.B//stateCurr === STATE_ERROR - crc.io.isEnable := io.send.fire & ( stateCurr === STATE_FRAME_HEADER | stateCurr === STATE_SUBMSG_HEADER | stateCurr === STATE_SUBMSG_DATA | stateCurr === STATE_SUBMSG_TAIL ) - - - - crc.io.flush := stateCurr === STATE_IDLE | io.flush - - val frameInfo = RegInit(0.U.asTypeOf(new FrameHeader)) val subMsgHeadInfo = RegInit(0.U.asTypeOf(new SubMsgTxInfo)) val subMsgTailInfo = RegInit(0.U.asTypeOf(new SubMsgTail)) - - - when( io.frameReq.fire ){ frameInfo := io.frameReq.bits } @@ -86,8 +71,6 @@ class SlaveSendGen extends Module with RequireAsyncReset{ subMsgTailInfo := io.subMsgTailReq.bits } - - val lengthCnt = RegInit(0.U(12.W)) val frameLenCnt = RegInit(0.U(12.W)) @@ -99,15 +82,12 @@ class SlaveSendGen extends Module with RequireAsyncReset{ } } - when( stateCurr =/= stateNext ){ lengthCnt := 0.U } .elsewhen(io.send.fire){ lengthCnt := lengthCnt + 1.U } - - io.frameReq.ready := true.B io.subMsgHeadReq.ready := stateCurr =/= STATE_SUBMSG_HEADER & stateNext === STATE_SUBMSG_HEADER io.subMsgTailReq.ready := stateCurr =/= STATE_SUBMSG_TAIL & stateNext === STATE_SUBMSG_TAIL @@ -137,7 +117,6 @@ class SlaveSendGen extends Module with RequireAsyncReset{ ), STATE_SUBMSG_TAIL ), (stateCurr === STATE_CRC) -> Mux( io.send.fire, Mux( lengthCnt === (4-1).U, STATE_IDLE, STATE_CRC ), STATE_CRC), - // (stateCurr === STATE_ERROR) -> Mux( io.send.fire, STATE_IDLE, STATE_ERROR), (stateCurr === STATE_WAIT) -> Mux( io.subMsgHeadReq.valid, STATE_SUBMSG_HEADER, STATE_WAIT), )) ) @@ -149,7 +128,6 @@ class SlaveSendGen extends Module with RequireAsyncReset{ assert( ~(io.data(1).ready & ~io.data(1).valid) ) - io.send.valid := (stateCurr === STATE_FRAME_HEADER) | (stateCurr === STATE_SUBMSG_HEADER) | @@ -157,7 +135,6 @@ class SlaveSendGen extends Module with RequireAsyncReset{ (stateCurr === STATE_SUBMSG_TAIL) | (stateCurr === STATE_CRC) - val tdata_frame_header = Mux1H(Seq( (lengthCnt === 0.U) -> frameInfo.frameLenAim(11,4), (lengthCnt === 1.U) -> Cat( frameInfo.frameLenAim(3,0), 0.U(2.W), frameInfo.frameStyle), @@ -207,9 +184,7 @@ class SlaveSendGen extends Module with RequireAsyncReset{ (stateCurr === STATE_CRC) -> tdata_crc, )) - io.send.bits.tuser := false.B//(stateCurr === STATE_ERROR & stateNext === STATE_IDLE) - io.send.bits.tlast := (stateCurr === STATE_CRC & stateNext === STATE_IDLE) //|| (stateCurr === STATE_ERROR & stateNext === STATE_IDLE) - - + io.send.bits.tuser := false.B + io.send.bits.tlast := (stateCurr === STATE_CRC & stateNext === STATE_IDLE) } \ No newline at end of file diff --git a/src/main/scala/backBoard/shin/SpiInterface.scala b/src/main/scala/backBoard/shin/SpiInterface.scala index d06a152..3b40b9f 100644 --- a/src/main/scala/backBoard/shin/SpiInterface.scala +++ b/src/main/scala/backBoard/shin/SpiInterface.scala @@ -74,16 +74,6 @@ abstract class SpiInterfaceBase extends Module with RequireAsyncReset{ } - - - - - - - - - - } class SSpiInterface extends SpiInterfaceBase{ diff --git a/src/main/scala/backBoard/ebus/b4b5.scala b/src/main/scala/backBoard/shin/b4b5.scala similarity index 96% rename from src/main/scala/backBoard/ebus/b4b5.scala rename to src/main/scala/backBoard/shin/b4b5.scala index 4283cba..6540bc3 100644 --- a/src/main/scala/backBoard/ebus/b4b5.scala +++ b/src/main/scala/backBoard/shin/b4b5.scala @@ -1,78 +1,78 @@ -package BACK - -import chisel3._ -import chisel3.util._ - - -object b4b5Encoder{ - def apply( enq: UInt ): UInt = { - Mux1H(Seq( - (enq === "b0000".U) -> "b11110".U(5.W), - (enq === "b0001".U) -> "b01001".U(5.W), - (enq === "b0010".U) -> "b10100".U(5.W), - (enq === "b0011".U) -> "b10101".U(5.W), - (enq === "b0100".U) -> "b01010".U(5.W), - (enq === "b0101".U) -> "b01011".U(5.W), - (enq === "b0110".U) -> "b01110".U(5.W), - (enq === "b0111".U) -> "b01111".U(5.W), - (enq === "b1000".U) -> "b10010".U(5.W), - (enq === "b1001".U) -> "b10011".U(5.W), - (enq === "b1010".U) -> "b10110".U(5.W), - (enq === "b1011".U) -> "b10111".U(5.W), - (enq === "b1100".U) -> "b11010".U(5.W), - (enq === "b1101".U) -> "b11011".U(5.W), - (enq === "b1110".U) -> "b11100".U(5.W), - (enq === "b1111".U) -> "b11101".U(5.W), - )) - } -} - -object b4b5Decoder{ - def apply( enq: UInt ): UInt = { - Mux1H(Seq( - (enq === "b11110".U) -> "b0000".U(4.W), - (enq === "b01001".U) -> "b0001".U(4.W), - (enq === "b10100".U) -> "b0010".U(4.W), - (enq === "b10101".U) -> "b0011".U(4.W), - (enq === "b01010".U) -> "b0100".U(4.W), - (enq === "b01011".U) -> "b0101".U(4.W), - (enq === "b01110".U) -> "b0110".U(4.W), - (enq === "b01111".U) -> "b0111".U(4.W), - (enq === "b10010".U) -> "b1000".U(4.W), - (enq === "b10011".U) -> "b1001".U(4.W), - (enq === "b10110".U) -> "b1010".U(4.W), - (enq === "b10111".U) -> "b1011".U(4.W), - (enq === "b11010".U) -> "b1100".U(4.W), - (enq === "b11011".U) -> "b1101".U(4.W), - (enq === "b11100".U) -> "b1110".U(4.W), - (enq === "b11101".U) -> "b1111".U(4.W), - )) - } -} - -object Dualb4b5Encoder{ - def apply( enq: UInt ): UInt = { - require( enq.getWidth == 8, "Require Failed @ Dualb4b5Encoder!" ) - Cat( b4b5Encoder(enq(7,4)), b4b5Encoder(enq(3,0)) ) - } -} - -object Dualb4b5Decoder{ - def apply( enq: UInt ): UInt = { - require( enq.getWidth == 10, "Require Failed @ Dualb4b5Decoder!" ) - Cat( b4b5Decoder(enq(9,5)), b4b5Decoder(enq(4,0)) ) - } -} - - -class b4b5DualEncode extends Module with RequireAsyncReset{ - val io = IO(new Encode_Bundle) - - io.dataOut := Dualb4b5Encoder(io.dataIn) -} - -class b4b5DualDecode extends Module with RequireAsyncReset{ - val io = IO(new Decode_Bundle) - - io.dataOut := Dualb4b5Decoder(io.dataIn) -} +package BACK + +import chisel3._ +import chisel3.util._ + + +object b4b5Encoder{ + def apply( enq: UInt ): UInt = { + Mux1H(Seq( + (enq === "b0000".U) -> "b11110".U(5.W), + (enq === "b0001".U) -> "b01001".U(5.W), + (enq === "b0010".U) -> "b10100".U(5.W), + (enq === "b0011".U) -> "b10101".U(5.W), + (enq === "b0100".U) -> "b01010".U(5.W), + (enq === "b0101".U) -> "b01011".U(5.W), + (enq === "b0110".U) -> "b01110".U(5.W), + (enq === "b0111".U) -> "b01111".U(5.W), + (enq === "b1000".U) -> "b10010".U(5.W), + (enq === "b1001".U) -> "b10011".U(5.W), + (enq === "b1010".U) -> "b10110".U(5.W), + (enq === "b1011".U) -> "b10111".U(5.W), + (enq === "b1100".U) -> "b11010".U(5.W), + (enq === "b1101".U) -> "b11011".U(5.W), + (enq === "b1110".U) -> "b11100".U(5.W), + (enq === "b1111".U) -> "b11101".U(5.W), + )) + } +} + +object b4b5Decoder{ + def apply( enq: UInt ): UInt = { + Mux1H(Seq( + (enq === "b11110".U) -> "b0000".U(4.W), + (enq === "b01001".U) -> "b0001".U(4.W), + (enq === "b10100".U) -> "b0010".U(4.W), + (enq === "b10101".U) -> "b0011".U(4.W), + (enq === "b01010".U) -> "b0100".U(4.W), + (enq === "b01011".U) -> "b0101".U(4.W), + (enq === "b01110".U) -> "b0110".U(4.W), + (enq === "b01111".U) -> "b0111".U(4.W), + (enq === "b10010".U) -> "b1000".U(4.W), + (enq === "b10011".U) -> "b1001".U(4.W), + (enq === "b10110".U) -> "b1010".U(4.W), + (enq === "b10111".U) -> "b1011".U(4.W), + (enq === "b11010".U) -> "b1100".U(4.W), + (enq === "b11011".U) -> "b1101".U(4.W), + (enq === "b11100".U) -> "b1110".U(4.W), + (enq === "b11101".U) -> "b1111".U(4.W), + )) + } +} + +object Dualb4b5Encoder{ + def apply( enq: UInt ): UInt = { + require( enq.getWidth == 8, "Require Failed @ Dualb4b5Encoder!" ) + Cat( b4b5Encoder(enq(7,4)), b4b5Encoder(enq(3,0)) ) + } +} + +object Dualb4b5Decoder{ + def apply( enq: UInt ): UInt = { + require( enq.getWidth == 10, "Require Failed @ Dualb4b5Decoder!" ) + Cat( b4b5Decoder(enq(9,5)), b4b5Decoder(enq(4,0)) ) + } +} + + +class b4b5DualEncode extends Module with RequireAsyncReset{ + val io = IO(new Encode_Bundle) + + io.dataOut := Dualb4b5Encoder(io.dataIn) +} + +class b4b5DualDecode extends Module with RequireAsyncReset{ + val io = IO(new Decode_Bundle) + + io.dataOut := Dualb4b5Decoder(io.dataIn) +} diff --git a/src/main/scala/backBoard/ebus/b8b10.scala b/src/main/scala/backBoard/shin/b8b10.scala similarity index 100% rename from src/main/scala/backBoard/ebus/b8b10.scala rename to src/main/scala/backBoard/shin/b8b10.scala diff --git a/src/main/scala/backBoard/ebus/crc32.scala b/src/main/scala/backBoard/shin/crc32.scala similarity index 62% rename from src/main/scala/backBoard/ebus/crc32.scala rename to src/main/scala/backBoard/shin/crc32.scala index a131189..82916a4 100644 --- a/src/main/scala/backBoard/ebus/crc32.scala +++ b/src/main/scala/backBoard/shin/crc32.scala @@ -4,73 +4,6 @@ import chisel3._ import chisel3.util._ -// module eth_crc (Clk, Reset, Data, Enable, Initialize, Crc, CrcError); - - -// input Clk; -// input Reset; - // input [3:0] Data; - // input Enable; - // input Initialize; - - // output [31:0] Crc; -// output CrcError; - -// reg [31:0] Crc; - -// wire [31:0] CrcNext; - - -// assign CrcNext[0] = Enable & (Data[0] ^ Crc[28]); -// assign CrcNext[1] = Enable & (Data[1] ^ Data[0] ^ Crc[28] ^ Crc[29]); -// assign CrcNext[2] = Enable & (Data[2] ^ Data[1] ^ Data[0] ^ Crc[28] ^ Crc[29] ^ Crc[30]); -// assign CrcNext[3] = Enable & (Data[3] ^ Data[2] ^ Data[1] ^ Crc[29] ^ Crc[30] ^ Crc[31]); -// assign CrcNext[4] = (Enable & (Data[3] ^ Data[2] ^ Data[0] ^ Crc[28] ^ Crc[30] ^ Crc[31])) ^ Crc[0]; -// assign CrcNext[5] = (Enable & (Data[3] ^ Data[1] ^ Data[0] ^ Crc[28] ^ Crc[29] ^ Crc[31])) ^ Crc[1]; -// assign CrcNext[6] = (Enable & (Data[2] ^ Data[1] ^ Crc[29] ^ Crc[30])) ^ Crc[ 2]; -// assign CrcNext[7] = (Enable & (Data[3] ^ Data[2] ^ Data[0] ^ Crc[28] ^ Crc[30] ^ Crc[31])) ^ Crc[3]; -// assign CrcNext[8] = (Enable & (Data[3] ^ Data[1] ^ Data[0] ^ Crc[28] ^ Crc[29] ^ Crc[31])) ^ Crc[4]; -// assign CrcNext[9] = (Enable & (Data[2] ^ Data[1] ^ Crc[29] ^ Crc[30])) ^ Crc[5]; -// assign CrcNext[10] = (Enable & (Data[3] ^ Data[2] ^ Data[0] ^ Crc[28] ^ Crc[30] ^ Crc[31])) ^ Crc[6]; -// assign CrcNext[11] = (Enable & (Data[3] ^ Data[1] ^ Data[0] ^ Crc[28] ^ Crc[29] ^ Crc[31])) ^ Crc[7]; -// assign CrcNext[12] = (Enable & (Data[2] ^ Data[1] ^ Data[0] ^ Crc[28] ^ Crc[29] ^ Crc[30])) ^ Crc[8]; -// assign CrcNext[13] = (Enable & (Data[3] ^ Data[2] ^ Data[1] ^ Crc[29] ^ Crc[30] ^ Crc[31])) ^ Crc[9]; -// assign CrcNext[14] = (Enable & (Data[3] ^ Data[2] ^ Crc[30] ^ Crc[31])) ^ Crc[10]; -// assign CrcNext[15] = (Enable & (Data[3] ^ Crc[31])) ^ Crc[11]; -// assign CrcNext[16] = (Enable & (Data[0] ^ Crc[28])) ^ Crc[12]; -// assign CrcNext[17] = (Enable & (Data[1] ^ Crc[29])) ^ Crc[13]; -// assign CrcNext[18] = (Enable & (Data[2] ^ Crc[30])) ^ Crc[14]; -// assign CrcNext[19] = (Enable & (Data[3] ^ Crc[31])) ^ Crc[15]; -// assign CrcNext[20] = Crc[16]; -// assign CrcNext[21] = Crc[17]; -// assign CrcNext[22] = (Enable & (Data[0] ^ Crc[28])) ^ Crc[18]; -// assign CrcNext[23] = (Enable & (Data[1] ^ Data[0] ^ Crc[29] ^ Crc[28])) ^ Crc[19]; -// assign CrcNext[24] = (Enable & (Data[2] ^ Data[1] ^ Crc[30] ^ Crc[29])) ^ Crc[20]; -// assign CrcNext[25] = (Enable & (Data[3] ^ Data[2] ^ Crc[31] ^ Crc[30])) ^ Crc[21]; -// assign CrcNext[26] = (Enable & (Data[3] ^ Data[0] ^ Crc[31] ^ Crc[28])) ^ Crc[22]; -// assign CrcNext[27] = (Enable & (Data[1] ^ Crc[29])) ^ Crc[23]; -// assign CrcNext[28] = (Enable & (Data[2] ^ Crc[30])) ^ Crc[24]; -// assign CrcNext[29] = (Enable & (Data[3] ^ Crc[31])) ^ Crc[25]; -// assign CrcNext[30] = Crc[26]; -// assign CrcNext[31] = Crc[27]; - - -// always @ (posedge Clk or posedge Reset) -// begin -// if (Reset) -// Crc <= 32'hffffffff; -// else -// if(Initialize) -// Crc <= 32'hffffffff; -// else -// Crc <= CrcNext; -// end - -// assign CrcError = Crc[31:0] != 32'hc704dd7b; // CRC not equal to magic number - -// endmodule - - //----------------------------------------------------------------------------- // Copyright (C) 2009 OutputLogic.com // This source file may be used and distributed without restriction