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代码整理

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This commit is contained in:
RuigeLee
2025-09-11 11:50:58 +08:00
parent 2969cf70a1
commit d46e06d5b0
15 changed files with 506 additions and 964 deletions
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12
src/main/scala/backBoard/shin/MstSlvSwitch.scala
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@@ -352,9 +352,6 @@ trait MstSlvSwitchMaster{ this: MstSlvSwitchBase =>
}
masterParser.io.req := interface.io.txReq.valid
// masterParser.io.req.bits.txLength := interface.io.txReq.bits.txLength
// io.rsp := masterParser.io.rsp
masterParser.io.cReg := interface.io.cReg
masterParser.io.mReg := interface.io.mReg
@@ -440,9 +437,6 @@ trait MstSlvSwitchSlave{ this: MstSlvSwitchBase =>
interface.io.localDevIndex := slaveParser.io.localDevIndex
//从站链路寄存器
// interface.io.isDevOnLeft := slaveParser.io.isDevOnLeft
// interface.io.isDevOnLeftModify := slaveParser.io.isDevOnLeftModify
// interface.io.indexOfLeftDev := slaveParser.io.indexOfLeftDev
interface.io.isDevOnRight := slaveParser.io.isDevOnRight
interface.io.isDevOnRightModify := slaveParser.io.isDevOnRightModify
interface.io.indexOfRightDev := slaveParser.io.indexOfRightDev
@@ -627,12 +621,6 @@ trait MstSlvSwitchCDRIn{ this: MstSlvSwitchBase =>
val cdrSelC = interface.io.cReg.cdrParam === 2.U
val cdrSelA = ~cdrSelB & ~cdrSelC
// val downCDRSampleIn = Vec(3, Flipped(new CDRInSampleIO) )
// val upCDRSampleIn = Vec(3, Flipped(new CDRInSampleIO) )
when(cdrSelB){
io.downCDRSampleIn(1).serDat := downInSerDat
io.upCDRSampleIn(1).serDat := upInSerDat