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代码整理

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This commit is contained in:
RuigeLee
2025-09-11 11:50:58 +08:00
parent 2969cf70a1
commit d46e06d5b0
15 changed files with 506 additions and 964 deletions
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305
src/main/scala/backBoard/shin/CDRIn.scala Normal file
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@@ -0,0 +1,305 @@
package BACK
import chisel3._
import chisel3.util._
class CDRInSampleIO extends Bundle{
val serDat = Input(Bool())
val syncSerDat = Output(Bool())
}
class CDRInMultiSample extends Module with RequireAsyncReset{
val io: CDRInSampleIO = IO(new CDRInSampleIO)
val clkNum: Int = 16
require( clkNum == 16 )
//multiCLK 需要按照滞后相位接线，即0为最先到达，1次先
val multiCLK = IO(Input(Vec(clkNum, Bool())))
val sampleReg = Wire(Vec(clkNum, Bool()))
dontTouch(sampleReg)
for( i <- 0 until clkNum ) {
sampleReg(i) := withClockAndReset(multiCLK(i).asClock, reset.asBool){ ShiftRegister( io.serDat, 2, false.B, true.B ) }
}
val sampleReg_sync = for( i <- 0 until clkNum ) yield {
ShiftRegisters(sampleReg(i), 8)
}
for( i <- 0 until clkNum; j <- 0 until 8 ){dontTouch(sampleReg_sync(i)(j))}
val sampleReg_Align = Wire(Vec(8*clkNum,Bool()))
dontTouch(sampleReg_Align)
for( i <- 0 until clkNum ){
sampleReg_Align(i) := sampleReg_sync(i)(7)
}
for( i <- clkNum until 2*clkNum ){
sampleReg_Align(i) := sampleReg_sync(i-clkNum)(6)
}
for( i <- 2*clkNum until 3*clkNum ){
sampleReg_Align(i) := sampleReg_sync(i-2*clkNum)(5)
}
for( i <- 3*clkNum until 4*clkNum ){
sampleReg_Align(i) := sampleReg_sync(i-3*clkNum)(4)
}
for( i <- 4*clkNum until 5*clkNum ){
sampleReg_Align(i) := sampleReg_sync(i-4*clkNum)(3)
}
for( i <- 5*clkNum until 6*clkNum ){
sampleReg_Align(i) := sampleReg_sync(i-5*clkNum)(2)
}
for( i <- 6*clkNum until 7*clkNum ){
sampleReg_Align(i) := sampleReg_sync(i-6*clkNum)(1)
}
for( i <- 7*clkNum until 8*clkNum ){
sampleReg_Align(i) := sampleReg_sync(i-7*clkNum)(0)
}
val flitReg =
for( i <- 1 until (8*clkNum)-1 ) yield {
(sampleReg_Align(i-1) & sampleReg_Align(i+0)) |
(sampleReg_Align(i-1) & sampleReg_Align(i+1)) |
(sampleReg_Align(i+0) & sampleReg_Align(i+1))
}
for( i <- 0 until (8*clkNum)-2 ) {dontTouch(flitReg(i))}
val clearCnt = RegInit(0.U(4.W))
val checkCnt = RegInit(0.U(4.W))
val arbCali = RegInit(0.U( (log2Ceil(8*clkNum)).W ))
val isLock = RegInit(false.B)
when( (7*clkNum until 8*clkNum).map{ i => sampleReg_Align(i)}.reduce(_|_) === false.B ){
when( clearCnt =/= 10.U ){
clearCnt := clearCnt + 1.U
}
} .otherwise{
clearCnt := 0.U
}
when( ~isLock ){
checkCnt := 0.U
} .otherwise{
checkCnt := checkCnt + 1.U
}
//优先级电路，优先选择跳变的后一相进行操作，电路上需要做成可调的
val checkWindow = Wire( Vec(6, Bool()) )
dontTouch(checkWindow)
checkWindow(0) :=
Mux1H( (0 until 116).map{ i =>
(arbCali === (i+2).U) -> flitReg(i)
})
checkWindow(1) :=
Mux1H( (1 until 117).map{ i =>
(arbCali === (i+1).U) -> flitReg(i)
})
checkWindow(2) :=
Mux1H( (2 until 118).map{ i =>
(arbCali === i.U) -> flitReg(i)
})
checkWindow(3) :=
Mux1H( (3 until 119).map{ i =>
(arbCali === (i-1).U) -> flitReg(i)
})
checkWindow(4) :=
Mux1H( (4 until 120).map{ i =>
(arbCali === (i-2).U) -> flitReg(i)
})
checkWindow(5) :=
Mux1H( (5 until 121).map{ i =>
(arbCali === (i-3).U) -> flitReg(i)
})
when( ~isLock ){
for( i <- 0 until 16 ){
val j = 50+16 - i - 1
when( flitReg(j) ^ flitReg(j+1) ){
arbCali := j.U
}
}
}.elsewhen( checkCnt.andR ){ //锁定之后，只允许每16cycle移动一相位
assert( arbCali >= 2.U && arbCali < 118.U )
when(
(checkWindow(0) ^ checkWindow(1)) |
(checkWindow(1) ^ checkWindow(2))
){
when( arbCali =/= 2.U ){
arbCali := arbCali - 1.U
}
} .elsewhen(
(checkWindow(3) ^ checkWindow(4)) |
(checkWindow(4) ^ checkWindow(5))
){
when( arbCali =/= 117.U ){
arbCali := arbCali + 1.U
}
}
}
when( ~isLock ){
for( i <- 0 until 16 ){
val j = 50+16 - i - 1
when( flitReg(j) ^ flitReg(j+1) ){
isLock := true.B
}
}
} .elsewhen( clearCnt === 10.U ){
isLock := false.B
}
val asyncSerDat =
Mux1H(
(for { i <- 2 until 118 } yield {
(arbCali === i.U) -> flitReg(i+(8))
})
)
io.syncSerDat := asyncSerDat
}
class CDRInAxisIO extends Bundle{
val axis = Decoupled(new AXIS_Bundle(8))
val decode = Flipped(new Decode_Bundle)
val syncSerDat = Input(Bool())
val flush = Input(Bool())
}
class CDRInAxis extends Module with RequireAsyncReset{
val io: CDRInAxisIO = IO(new CDRInAxisIO)
io.decode.dataIn := 0.U
def HeaderByte: Int = 4
val ETH_PRE = "h68".U(8.W)
val ETH_SFD = "h25".U(8.W)
val STATE_IDLE = 0.U
val STATE_HEADER = 1.U
val STATE_PAYLOAD = 2.U
val stateNext = Wire(UInt(2.W))
val stateCurr = RegNext( stateNext, STATE_IDLE )
val bitCnt = RegInit(0.U(4.W))
val byteCnt = RegInit(0.U((12+1).W))
val checkSFD = RegInit( 0.U(10.W) )
when( io.flush ){
checkSFD := 0.U
} .otherwise{
checkSFD := Cat( checkSFD(8,0), io.syncSerDat )
}
io.decode.dataIn := checkSFD(9,0)
val shiftData = io.decode.dataOut
val shiftData10Next = ShiftRegister( shiftData, 10, 0.U(8.W), true.B )
val payloadLen = RegInit(0.U(12.W))
when( io.flush ){
payloadLen := 0.U
} .elsewhen( byteCnt === 0.U & bitCnt === 9.U & stateCurr === STATE_HEADER ){
payloadLen := Cat( shiftData, 0.U(4.W) )
} .elsewhen( byteCnt === 1.U & bitCnt === 9.U & stateCurr === STATE_HEADER ){
payloadLen := Cat( payloadLen(11,4), shiftData(7,4) )
}
stateNext :=
Mux( io.flush, STATE_IDLE,
Mux1H(Seq(
(stateCurr === STATE_IDLE) -> ( Mux( shiftData10Next === ETH_PRE && shiftData === ETH_SFD , STATE_HEADER, STATE_IDLE )), //IDLE
(stateCurr === STATE_HEADER) -> ( Mux( (byteCnt === (HeaderByte-1).U) & (bitCnt === 9.U), STATE_PAYLOAD, STATE_HEADER ) ),
(stateCurr === STATE_PAYLOAD) -> ( Mux( (byteCnt === (payloadLen + (4 - 1).U) ) & (bitCnt === 9.U), STATE_IDLE, STATE_PAYLOAD )), // PAYLOAD
)) //crc
)
when( stateCurr === STATE_IDLE & ( shiftData10Next === ETH_PRE && shiftData === ETH_SFD ) ){ //first align
bitCnt := 0.U
} .otherwise{
when( bitCnt === 9.U ){
bitCnt := 0.U
} .otherwise{
bitCnt := bitCnt + 1.U
}
}
when( io.flush ){
byteCnt := 0.U
} .elsewhen( stateCurr === STATE_IDLE & ( shiftData10Next === ETH_PRE && shiftData === ETH_SFD ) ){ //first align
byteCnt := 0.U
} .elsewhen( bitCnt === 9.U ){
when( stateCurr === STATE_HEADER ){
byteCnt := Mux( byteCnt =/= (HeaderByte-1).U, byteCnt + 1.U, 0.U )
assert( byteCnt <= (HeaderByte-1).U )
} .elsewhen( stateCurr === STATE_PAYLOAD ){
byteCnt := Mux( byteCnt =/= (payloadLen+ (4-1).U), byteCnt + 1.U, 0.U )
assert( byteCnt <= ( payloadLen+ (4-1).U ) )
}
}
val axis_valid = RegInit(false.B)
val axis_tdata = RegEnable( shiftData, 0.U(8.W), bitCnt === 9.U & ( stateCurr === STATE_HEADER | stateCurr === STATE_PAYLOAD ) )
val axis_tuser = false.B
val axis_tlast = RegInit( false.B )
io.axis.valid := axis_valid
io.axis.bits.tdata := axis_tdata
io.axis.bits.tuser := axis_tuser
io.axis.bits.tlast := axis_tlast
when( io.flush ){
axis_valid := false.B
} .elsewhen( io.axis.fire ){
axis_valid := false.B
} .elsewhen( bitCnt === 9.U & ( stateCurr === STATE_HEADER | stateCurr === STATE_PAYLOAD ) ){
axis_valid := true.B
}
when( io.flush ){
axis_tlast := false.B
} .otherwise{
axis_tlast := (stateCurr === STATE_PAYLOAD & stateNext === STATE_IDLE)
}
}

117
src/main/scala/backBoard/shin/CDROut.scala Normal file
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@@ -0,0 +1,117 @@
package BACK
import chisel3._
import chisel3.util._
class AXIS_Bundle(dw: Int) extends Bundle{
val tdata = UInt(dw.W)
val tlast = Bool()
val tuser = Bool()
}
//work in 100MHZ
class CDROutIO extends Bundle{
val axis = Flipped(Decoupled(new AXIS_Bundle(8)))
val encode = Flipped(new Encode_Bundle)
val serDat = Output(Bool())
val flush = Input(Bool())
}
class CDROut extends Module with RequireAsyncReset{
val io: CDROutIO = IO(new CDROutIO)
def PRE_NUM = 3 //PRE_NUM should >= 3
def STATE_IDLE = 0.U
def STATE_PREAMBLE = 1.U
def STATE_PAYLOAD = 2.U
val ETH_PRE = "h68".U(8.W)
val ETH_SFD = "h25".U(8.W)
val stateNext = Wire(UInt(2.W))
val stateCurr = RegNext( stateNext, 0.U )
val bitCnt = RegInit(0.U(4.W))
val byteCnt = RegInit(0.U(3.W)) //payload dont need to count
val shiftData = RegInit(0.U(10.W))
io.encode.isEnable := false.B //组合逻辑
io.encode.dataIn := 0.U //组合逻辑
stateNext :=
Mux( io.flush, STATE_IDLE,
Mux1H(Seq(
(stateCurr === STATE_IDLE) -> ( Mux( io.axis.valid, STATE_PREAMBLE, STATE_IDLE )),
(stateCurr === STATE_PREAMBLE) -> ( Mux( (byteCnt === (PRE_NUM-1).U) & (bitCnt === 9.U), Mux( io.axis.valid, STATE_PAYLOAD, STATE_IDLE), STATE_PREAMBLE )),
(stateCurr === STATE_PAYLOAD) -> ( Mux( (io.axis.fire & io.axis.bits.tlast) | (~io.axis.valid & io.axis.ready), STATE_IDLE, STATE_PAYLOAD ) ),
))
)
io.serDat := shiftData.extract(9)
io.axis.ready :=
bitCnt === 9.U & (
(stateCurr === STATE_PREAMBLE & byteCnt === (PRE_NUM-1).U) |
(stateCurr === STATE_PAYLOAD)
)
// assert( ~(~io.axis.valid & io.axis.ready) )
when( ~io.axis.valid & io.axis.ready ){
printf( "Error, CDROut axis overflow!\n" )
}
when( io.flush ){
shiftData := 0.U
} .elsewhen( stateCurr === STATE_IDLE & stateNext === STATE_PREAMBLE){ //PRE
shiftData := io.encode.dataOut
io.encode.dataIn := ETH_PRE //组合逻辑
io.encode.isEnable := true.B //组合逻辑
} .otherwise{
when( bitCnt =/= 9.U ){
shiftData := shiftData << 1
} .otherwise{ //bitCnt === 9.U
when( stateCurr === STATE_PREAMBLE ){
shiftData := io.encode.dataOut
io.encode.dataIn := MuxCase( ETH_PRE, Array(
( byteCnt === (PRE_NUM-2).U ) -> ETH_SFD,
( byteCnt === (PRE_NUM-1).U ) -> io.axis.bits.tdata,
)) //组合逻辑
io.encode.isEnable := true.B //组合逻辑
} .elsewhen( stateCurr === STATE_PAYLOAD ){
io.encode.dataIn := io.axis.bits.tdata //组合逻辑
shiftData := io.encode.dataOut
io.encode.isEnable := true.B //组合逻辑
}
}
}
when( stateCurr === STATE_IDLE ){ //PRE
bitCnt := 0.U
} .otherwise{
when( bitCnt === 9.U ){
bitCnt := 0.U
} .otherwise{
bitCnt := bitCnt + 1.U
}
}
when( (stateCurr === STATE_IDLE) | (stateCurr === STATE_PAYLOAD) ){
byteCnt := 0.U
} .elsewhen( bitCnt === 9.U ){
byteCnt := byteCnt + 1.U
}
}

33
src/main/scala/backBoard/shin/Encryptor.scala Normal file
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@@ -0,0 +1,33 @@
package BACK
import chisel3._
import chisel3.util._
class Encryptor_IO_Bundle extends Bundle{
val init = Flipped(Valid(UInt(128.W)))
val op = Decoupled(UInt(8.W))
}
class Encryptor extends Module{
val io: Encryptor_IO_Bundle = IO(new Encryptor_IO_Bundle)
val encryptReg = RegInit(0.U(128.W))
when( io.init.valid ){
encryptReg := io.init.bits
} .elsewhen( io.op.fire ){
encryptReg := Cat(encryptReg(119,0), io.op.bits)
}
val opValid = RegInit(false.B)
when( io.init.fire ){
opValid := true.B
}
io.op.valid := opValid
io.op.bits := encryptReg(127, 120)
}

72
src/main/scala/backBoard/shin/Interface.scala
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@@ -255,8 +255,6 @@ abstract class InterfaceBase extends Module with RequireAsyncReset{
(addr === ("h10".U(16.W) + i.U) ) -> cReg.uniCode( 8*i+7,8*i+0 )
}) ++
Seq(
(addr === "h8".U ) -> cReg.busRate( 7,0 ),
(addr === "h9".U ) -> cReg.spiSel,
@@ -264,25 +262,14 @@ abstract class InterfaceBase extends Module with RequireAsyncReset{
(addr === "hb".U & isSlvMode) -> sReg.localDevIndex(15,8),
) ++
Seq(
(addr === "h18".U ) -> sReg.lvdsWriteAble.extract(0),
(addr === "h20".U & isMstMode) -> Cat(mReg.rxSM, mReg.txSM, 0.U(1.W) ),
(addr === "h22".U & isMstMode) -> mReg.isRecCRCErr,
//(addr === "h21".U & isMstMode) -> mReg.txLength,
(addr === "h24".U & isMstMode) -> mReg.rplTimeStampTx(7,0),
(addr === "h25".U & isMstMode) -> mReg.rplTimeStampTx(15,8),
) ++
Seq(
(addr === "h40".U ) -> cReg.softResetCode(1),
(addr === "h41".U ) -> cReg.softResetCode(1),
@@ -374,14 +361,9 @@ abstract class InterfaceBase extends Module with RequireAsyncReset{
(addr === "hb6".U ) -> cReg.statUpRecByteCnt(55,48),
(addr === "hb7".U ) -> cReg.statUpRecByteCnt(63,56),
(addr === "hc0".U ) -> Cat( sReg.isDevOnRightModify, sReg.isDevOnRight, 0.U(3.W) ),
(addr === "hc2".U ) -> sReg.indexOfRightDev(7,0),
(addr === "hc3".U ) -> sReg.indexOfRightDev(13,8),
// (addr === "hc4".U ) -> sReg.indexOfLeftDev(7,0),
// (addr === "hc5".U ) -> sReg.indexOfLeftDev(13,8),
) ++
Seq(
@@ -500,18 +482,12 @@ abstract class InterfaceBase extends Module with RequireAsyncReset{
)}.reduce(_++_) ++
( 0 until 8 ).map{ i =>
( addr === ("h301".U(16.W) + (i*4).U) ) -> cReg.smUsedDepth(i)
} ++
( 0 until 8 ).map{ i =>
( addr === ("h302".U(16.W) + (i*4).U) ) -> cReg.smTrigLen(i)(7,0)
} ++
( 0 until 8 ).map{ i =>
( addr === ("h303".U(16.W) + (i*4).U) ) -> cReg.smTrigLen(i)(10,8)
} ++
( 0 until 4 ).map{ i =>
( addr === ("h400".U(16.W) + i.U) ) -> cReg.wdtStatus( 8*i+7, 8*i+0 )
} ++
( 0 until 4 ).map{ i =>
( addr === ("h404".U(16.W) + i.U) ) -> cReg.wdtEnable( 8*i+7, 8*i+0 )
} ++
(for( i <- 0 until 17; j <- 0 until 4 ) yield {
@@ -525,26 +501,12 @@ abstract class InterfaceBase extends Module with RequireAsyncReset{
) ++
( 0 until 8 ).map{ i =>
( addr === ("h508".U(16.W) + i.U) ) -> cReg.event.posedgeTimeStampLatch(0)( 8*i+7, 8*i+0 )
} ++
( 0 until 8 ).map{ i =>
( addr === ("h510".U(16.W) + i.U) ) -> cReg.event.negedgeTimeStampLatch(0)( 8*i+7, 8*i+0 )
} ++
( 0 until 8 ).map{ i =>
( addr === ("h518".U(16.W) + i.U) ) -> cReg.event.posedgeTimeStampLatch(1)( 8*i+7, 8*i+0 )
} ++
( 0 until 8 ).map{ i =>
( addr === ("h520".U(16.W) + i.U) ) -> cReg.event.negedgeTimeStampLatch(1)( 8*i+7, 8*i+0 )
} ++
( 0 until 8 ).map{ i =>
( addr === ("h528".U(16.W) + i.U) ) -> cReg.event.mcuSMTimeStampEnq( 8*i+7, 8*i+0 )
} ++
( 0 until 8 ).map{ i =>
( addr === ("h530".U(16.W) + i.U) ) -> cReg.event.mcuSMTimeStampDeq( 8*i+7, 8*i+0 )
} ++
( 0 until 8 ).map{ i =>
( addr === ("h538".U(16.W) + i.U) ) -> cReg.event.lvdsSMTimeStampEnq( 8*i+7, 8*i+0 )
} ++
( 0 until 8 ).map{ i =>
( addr === ("h540".U(16.W) + i.U) ) -> cReg.event.lvdsSMTimeStampDeq( 8*i+7, 8*i+0 )
} ++
Seq()
@@ -569,12 +531,6 @@ abstract class InterfaceBase extends Module with RequireAsyncReset{
trait InterfaceMCUop{ this: InterfaceBase =>
isEnW := Mux1H(Seq(
( cReg.spiSel === 0.U ) -> iQSpi.io.isEnW,
( cReg.spiSel === 1.U ) -> oSpi.io.isEnW,
@@ -638,7 +594,6 @@ trait InterfaceMCUop{ this: InterfaceBase =>
mReg.txSM := RegEnable( dataw(2,1), 0.U(2.W), isEnW & addrw === "h20".U )
mReg.rxSM := RegEnable( dataw(4,3), 0.U(2.W), isEnW & addrw === "h20".U )
// mReg.txLength := Cat( RegEnable( dataw, 0.U, isEnW & addrw === "h22".U ), RegEnable( dataw, 0.U, isEnW & addrw === "h21".U ) )
val mReg_isRecCRCErr = RegInit(0.U(4.W))
mReg.isRecCRCErr := mReg_isRecCRCErr
@@ -680,7 +635,6 @@ trait InterfaceCheckSM{ this: InterfaceBase =>
for( i <- 0 until 8 ){
io.isSMReset(i) := isEnW & (addrw === ("h300".U(16.W) + (i*4).U))
cReg.smUsedDepth(i) := io.smUsedDepth(i)
@@ -699,10 +653,6 @@ trait InterfaceCheckSM{ this: InterfaceBase =>
smTrigLen_L(i) := io.lvds.dataw
}
}
}
@@ -746,8 +696,6 @@ trait InterfaceEBMMU{ this: InterfaceBase =>
io.lvds.datar := RegEnable(AcquireReg(addr = io.lvds.addrr), 0.U(8.W), io.lvds.isEnR)
( 0 until 16 ).map{ i =>
sReg.ebmmu(i).lAddr := Cat(
RegEnable( io.lvds.dataw(5,0), 0.U(8.W), sReg.isLVDSWriteAble & io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h203".U(16.W) + (10*i).U )) ),
@@ -1040,8 +988,8 @@ trait InterfaceWdt{ this: InterfaceBase =>
cReg.wdtEnable :=
Cat(
RegEnable( dataw(1,0), 0.U(2.W), isEnW & addrw === "h406".U ),
RegEnable( dataw, 0.U(8.W), isEnW & addrw === "h405".U ),
RegEnable( dataw, 0.U(8.W), isEnW & addrw === "h404".U ),
RegEnable( dataw, 0.U(8.W), isEnW & addrw === "h405".U ),
RegEnable( dataw, 0.U(8.W), isEnW & addrw === "h404".U ),
)
for( i <- 0 until 18 ){
@@ -1145,9 +1093,6 @@ trait InterfaceInterrupt{ this: InterfaceBase =>
intStatus(4) := true.B
}
//从站SM请求
for( i <- 0 until 8 ){
when( io.intSlvTrig(i) ){
@@ -1398,11 +1343,6 @@ trait InterfaceStat{ this: InterfaceBase =>
statDownRecByteCnt := statDownRecByteCnt + 1.U
}
when(io.lvds.isEnW & (io.lvds.addrw === "ha0".U )){
statUpRecErrorCnt := 0.U
} .elsewhen( io.upRecStat.isRecError ){
@@ -1475,10 +1415,7 @@ with InterfaceAnalog
io.txReq.bits.txSM := mReg.txSM
io.txReq.bits.rxSM := mReg.rxSM
// io.txReq.bits.txLength := //mReg.txLength
io.txReq.valid := RegNext(isEnW & addrw === "h20".U & dataw.extract(0) === "b1".U, false.B) //& mReg.txLength =/= 0.U
io.txReq.valid := RegNext(isEnW & addrw === "h20".U & dataw.extract(0) === "b1".U, false.B)
sReg.localDevIndex := io.localDevIndex
@@ -1487,6 +1424,5 @@ with InterfaceAnalog
sReg.isDevOnRightModify := io.isDevOnRightModify
sReg.indexOfRightDev := io.indexOfRightDev
}
}

16
src/main/scala/backBoard/shin/MasterParser.scala
View File

@@ -43,11 +43,6 @@ abstract class MasterParserBase extends Module with RequireAsyncReset{
val txcrc = Module(new crc32_8)
val rxcrc = Module(new crc32_8)
// io.req.ready := reqReady
when( io.req ){
reqReady := false.B
} .elsewhen( io.downOut.fire & txCnt === txLen + (4-1).U ){
@@ -134,8 +129,6 @@ abstract class MasterParserBase extends Module with RequireAsyncReset{
io.downOut.bits.tuser := false.B
io.downOut.bits.tlast := txCnt === (txLen + 3.U)
val recCrcCheck = RegInit(0.U(32.W))
when( io.req ){
@@ -154,16 +147,10 @@ abstract class MasterParserBase extends Module with RequireAsyncReset{
io.rsp.valid := io.upIn.fire & io.upIn.bits.tlast
io.rsp.bits.isError := io.upIn.fire & io.upIn.bits.tlast & (Cat( recCrcCheck(31,8), io.upIn.bits.tdata ) =/= rxcrc.io.crc)
// io.rsp.bits.length := rxCnt + 1.U
io.rxEnq := io.upIn.fire & io.upIn.bits.tlast
io.txDeq := io.downOut.fire & io.downOut.bits.tlast
txcrc.io.isEnable := io.downOut.fire & txCnt < txLen
txcrc.io.dataIn := io.downOut.bits.tdata
txcrc.io.flush := reqReady
@@ -172,8 +159,6 @@ abstract class MasterParserBase extends Module with RequireAsyncReset{
rxcrc.io.dataIn := io.upIn.bits.tdata
rxcrc.io.flush := io.rsp.fire
when( io.upIn.fire ){
when( rxCnt === rxLen ){
recCrcCheck := io.upIn.bits.tdata << 24
@@ -199,7 +184,6 @@ trait MasterParserStat{ this: MasterParserBase =>
io.upRecStat.isFinish := io.rsp.valid & ~io.rsp.bits.isError
io.upRecStat.isRecByteAck := io.upIn.fire
}
class MasterParser extends MasterParserBase

12
src/main/scala/backBoard/shin/MstSlvSwitch.scala
View File

@@ -352,9 +352,6 @@ trait MstSlvSwitchMaster{ this: MstSlvSwitchBase =>
}
masterParser.io.req := interface.io.txReq.valid
// masterParser.io.req.bits.txLength := interface.io.txReq.bits.txLength
// io.rsp := masterParser.io.rsp
masterParser.io.cReg := interface.io.cReg
masterParser.io.mReg := interface.io.mReg
@@ -440,9 +437,6 @@ trait MstSlvSwitchSlave{ this: MstSlvSwitchBase =>
interface.io.localDevIndex := slaveParser.io.localDevIndex
//从站链路寄存器
// interface.io.isDevOnLeft := slaveParser.io.isDevOnLeft
// interface.io.isDevOnLeftModify := slaveParser.io.isDevOnLeftModify
// interface.io.indexOfLeftDev := slaveParser.io.indexOfLeftDev
interface.io.isDevOnRight := slaveParser.io.isDevOnRight
interface.io.isDevOnRightModify := slaveParser.io.isDevOnRightModify
interface.io.indexOfRightDev := slaveParser.io.indexOfRightDev
@@ -627,12 +621,6 @@ trait MstSlvSwitchCDRIn{ this: MstSlvSwitchBase =>
val cdrSelC = interface.io.cReg.cdrParam === 2.U
val cdrSelA = ~cdrSelB & ~cdrSelC
// val downCDRSampleIn = Vec(3, Flipped(new CDRInSampleIO) )
// val upCDRSampleIn = Vec(3, Flipped(new CDRInSampleIO) )
when(cdrSelB){
io.downCDRSampleIn(1).serDat := downInSerDat
io.upCDRSampleIn(1).serDat := upInSerDat

147
src/main/scala/backBoard/shin/NSpiInterface.scala.bk
View File

@@ -1,147 +0,0 @@
package BACK
import chisel3._
import chisel3.util._
abstract class SyncSpiInterfaceBase extends Module with RequireAsyncReset{
val io = IO(new RegAccessInterfaceIO)
}
class SyncSSpiInterface extends SyncSpiInterfaceBase{
val spi = IO(new SSPIInterfaceIO)
// withClockAndReset(sck.asClock, reset.asBool){
spi.miso := exRego.extract(7)
val bitSel = withClockAndReset(spi.sck.asClock, spi.csn){RegInit(0.U(3.W)) }
val byteSel = withClockAndReset(spi.sck.asClock, spi.csn){RegInit(0.U(12.W))}
val exRego = withClockAndReset(spi.sck.asClock, spi.csn){RegInit(0.U(8.W))}
val exRegi = withClockAndReset(spi.sck.asClock, spi.csn){RegInit(0.U(8.W))}
when( true.B ){
bitSel := bitSel + 1.U
}
when( bitSel.andR ){
byteSel := byteSel + 1.U
}
when( true.B ){
exRegi := Cat( exRegi(6 ,0), spi.mosi )
}
when( bitSel === 0.U ){
when((byteSel === 1.U || byteSel === 2.U) ){
exRego := 0.U //地址1，cmd
} .elsewhen( isSpiRead ){
exRego := datar_async
}
}.otherwise{
exRego := exRego << 1
}
val addrw_async = withClockAndReset(spi.sck.asClock, spi.csn){ RegInit(0.U(16.W)) }
val addrr_async = withClockAndReset(spi.sck.asClock, spi.csn){ RegInit(0.U(16.W)) }
val dataw_async = withClockAndReset(spi.sck.asClock, spi.csn){ RegInit(0.U(8.W)) }
val datar_async = withClockAndReset(spi.sck.asClock, spi.csn){ RegInit(0.U(8.W)) }
val spiCmd = withClockAndReset(spi.sck.asClock, spi.csn){ RegInit(false.B) }
val isSpiWrite = ~spiCmd
val isSpiRead = spiCmd
when( bitSel === 0.U ){
when( byteSel === 1.U ){
addrw_async := exRegi
} .elsewhen( byteSel === 2.U ) {
addrw_async := Cat(addrw_async(7,0), exRegi)
} .elsewhen( byteSel > 3.U ){
addrw_async := addrw_async + 1.U
}
}
when( bitSel === 0.U ){
when( byteSel === 1.U ){
addrr_async := exRegi
} .elsewhen( byteSel === 2.U ) {
addrr_async := Cat(addrr_async(7,0), exRegi)
} .elsewhen( byteSel > 2.U ){
addrr_async := addrr_async + 1.U
}
}
when( byteSel === 2.U & bitSel === 0.U ){ //CS为低，且SCK上跳的第0byte
spiCmd := spi.mosi
}
when( bitSel === 0.U ){
when( byteSel > 3.U & isSpiWrite ){
dataw_async := exRegi
}
}
io.dataw := exRegi
io.addrr := Mux( isSpiRead, addrr + 1.U, addrr )
// io.addrSel :=
// Mux( isSpiRead, addrSel + 1.U, addrSel )//覆盖三种情况
// val readData = RegEnable(io.datar, io.isEnR)
isEnW_async
isEnR_async
addrw_async
addrr_async
datar_async
dataw_async
// isEnR_async := bitSel === 1.U & (byteSel >= 2.U) & isSpiRead
// isEnW_async := bitSel === 0.U & (byteSel >= 4.U) & isSpiWrite
val isEnWSet_async = withClockAndReset(spi.sck.asClock, spi.csn){ RegInit(false.B) }
val isEnWSet_sync = ShiftRegisters(isEnWSet_async, 3, false.B, true.B)
val isEnWReset_async = withClockAndReset(spi.sck.asClock, spi.csn){ ShiftRegister(isEnWSet_sync(1), 2, false.B, true.B) }
when( bitSel === 0.U & (byteSel >= 4.U) & isSpiWrite ){
assert( ~isEnWSet_async, "Assert Failed @spi!\n" )
isEnWSet_async := true.B
} .elsewhen(isEnWReSet_async){
isEnWSet_async := false.B
}
io.isEnW := ~isEnWSet_async(2) & isEnWSet_async(1)
io.addrw := addrw_async
io.dataw := dataw_async
val isEnRSet_async = withClockAndReset(spi.sck.asClock, spi.csn){ RegInit(false.B) }
val isEnRSet_sync = ShiftRegisters(isEnRSet_async, 3, false.B, true.B)
val isEnRReset_async = withClockAndReset(spi.sck.asClock, spi.csn){ ShiftRegister(isEnRSet_sync(1), 2, false.B, true.B) }
when( bitSel === 1.U & (byteSel >= 2.U) & isSpiRead ){
assert( ~isEnRSet_async, "Assert Failed @spi!\n" )
isEnRSet_async := true.B
} .elsewhen(isEnRReSet_async){
isEnRSet_async := false.B
}
io.isEnR := ~isEnRSet_async(2) & isEnRSet_async(1)
io.addrr := addrr_async
datar_async := withClockAndReset(spi.sck.asClock, spi.csn){ RegEnable(io.datar, 0.U, isEnRReSet_async }
}

85
src/main/scala/backBoard/shin/ShareSRAM.scala
View File

@@ -3,91 +3,6 @@ package BACK
import chisel3._
import chisel3.util._
class ShareSRAMDP extends BlackBox with HasBlackBoxInline {
class ShareSRAMDPIO extends Bundle{
val addrA = Input(UInt(15.W))
val datawA = Input( UInt(8.W) )
val datarA = Output( UInt(8.W) )
val enwA = Input(Bool())
val enrA = Input(Bool())
val clockA = Input(Bool())
val addrB = Input(UInt(15.W))
val datawB = Input( UInt(8.W) )
val datarB = Output( UInt(8.W) )
val enwB = Input(Bool())
val enrB = Input(Bool())
val clockB = Input(Bool())
}
val io: ShareSRAMDPIO = IO(new ShareSRAMDPIO)
setInline("ShareSRAMDP.v",
"""
| module ShareSRAMDP(
| input [7:0] datawA,
| input [14:0] addrA,
| input enwA,
| input enrA,
| output [7:0] datarA,
| input clockA,
|
| input [7:0] datawB,
| input [14:0] addrB,
| input enwB,
| input enrB,
| output [7:0] datarB,
| input clockB
| );
|
| reg [7:0] mem[0:32767];
| reg [7:0] data_outa_reg = 8'b0;
| reg [7:0] data_outb_reg = 8'b0;
|
| assign datarA = data_outa_reg;
| assign datarB = data_outb_reg;
|
| always@( posedge clockA ) begin
| if( enrA ) begin
| end
|
| if( enwA ) begin
| mem[addrA] <= datawA;
| end else begin
| data_outa_reg <= mem[addrA];
| end
| end
|
|
| always@( posedge clockB ) begin
| if(enrB) begin
| end
|
| if( enwB ) begin
| mem[addrB] <= datawB;
| end else begin
| data_outb_reg <= mem[addrB];
| end
| end
|
| initial begin
| for( integer i = 0; i < 32768; i = i + 1 ) begin
| mem[i] = $random;
| end
| end
|
|
|endmodule
""".stripMargin)
}
class ShareSRAM2k extends BlackBox with HasBlackBoxInline {
class ShareSRAM2kIO extends Bundle{

14
src/main/scala/backBoard/shin/SlaveParser.scala
View File

@@ -26,17 +26,6 @@ class SubMsgTail extends Bundle{
val workCnt = UInt(16.W) //子报文工作计数
}
// class ShareSRAMIO extends Bundle{
// val addr = Input(UInt(15.W))
// val dataw = Input( UInt(8.W) )
// val datar = Output( UInt(8.W) )
// val enw = Input(Bool())
// val enr = Input(Bool())
// }
class SlaveParserIO extends Bundle{
val downIn = Flipped( Decoupled(new AXIS_Bundle(8)) )
val downOut = Decoupled(new AXIS_Bundle(8))
@@ -56,9 +45,6 @@ class SlaveParserIO extends Bundle{
val localDevIndex = Output(UInt(16.W))
//开放链路寄存器组给interface
// val isDevOnLeft = Output(UInt(2.W))
// val isDevOnLeftModify = Output(Bool())
// val indexOfLeftDev = Output(UInt(14.W))
val isDevOnRight = Output(UInt(2.W))
val isDevOnRightModify = Output(Bool())
val indexOfRightDev = Output(UInt(14.W))

18
src/main/scala/backBoard/shin/SlaveRecParser.scala
View File

@@ -65,17 +65,9 @@ class SlaveRecParser extends Module with RequireAsyncReset{
val FRAME_STYLE_COMMON = 0.U
val FRAME_STYLE_PROBE = 1.U
val lengthCnt = RegInit(0.U(12.W)) //动态计数器
val frameLenCnt = RegInit(0.U(12.W)) //帧长度计数
io.frameReq.valid := (stateCurr === STATE_HEADER) & (stateNext === STATE_SUBMSG_HEADER | stateNext === STATE_CRC)
val frameHeader = RegInit(0.U.asTypeOf(new FrameHeader))
io.frameReq.bits.frameLenAim := frameHeader.frameLenAim
@@ -172,12 +164,6 @@ class SlaveRecParser extends Module with RequireAsyncReset{
}
}
stateNext :=
Mux( io.flush, STATE_IDLE,
Mux1H(Seq(
@@ -212,10 +198,6 @@ class SlaveRecParser extends Module with RequireAsyncReset{
))
)
io.stat.isHeaderError := stateNext === STATE_ERROR & stateCurr === STATE_HEADER
io.stat.isSubHeaderError := stateNext === STATE_ERROR & stateCurr === STATE_SUBMSG_HEADER
io.stat.isPayloadError := stateNext === STATE_ERROR & stateCurr === STATE_PAYLOAD_DATA

29
src/main/scala/backBoard/shin/SlaveSendGen.scala
View File

@@ -12,15 +12,12 @@ class SubMsgTxInfo extends SubMsgHeader{
class SlaveSendGenIO extends Bundle{
val data = Vec(2, Flipped( Decoupled(UInt(8.W)) ) )
val frameReq = Flipped(Decoupled( new FrameHeader ))
val subMsgHeadReq = Flipped(Decoupled( new SubMsgTxInfo ))
val subMsgTailReq = Flipped(Decoupled( new SubMsgTail ))
val send = Decoupled(new AXIS_Bundle(8))
val isError = Output(Bool())
val stateCurr = Output(UInt(3.W))
val flush = Input(Bool())
@@ -32,7 +29,6 @@ class SlaveSendGenIO extends Bundle{
class SlaveSendGen extends Module with RequireAsyncReset{
val io: SlaveSendGenIO = IO(new SlaveSendGenIO)
val crc = Module(new crc32_8)
val FRAME_STYLE_COMMON = 0.U
@@ -50,30 +46,19 @@ class SlaveSendGen extends Module with RequireAsyncReset{
val stateNext = Wire(UInt(3.W))
val stateCurr = RegNext(stateNext, STATE_IDLE); io.stateCurr := stateCurr
io.isError := false.B//stateCurr === STATE_ERROR
crc.io.isEnable := io.send.fire & (
stateCurr === STATE_FRAME_HEADER |
stateCurr === STATE_SUBMSG_HEADER |
stateCurr === STATE_SUBMSG_DATA |
stateCurr === STATE_SUBMSG_TAIL
)
crc.io.flush := stateCurr === STATE_IDLE | io.flush
val frameInfo = RegInit(0.U.asTypeOf(new FrameHeader))
val subMsgHeadInfo = RegInit(0.U.asTypeOf(new SubMsgTxInfo))
val subMsgTailInfo = RegInit(0.U.asTypeOf(new SubMsgTail))
when( io.frameReq.fire ){
frameInfo := io.frameReq.bits
}
@@ -86,8 +71,6 @@ class SlaveSendGen extends Module with RequireAsyncReset{
subMsgTailInfo := io.subMsgTailReq.bits
}
val lengthCnt = RegInit(0.U(12.W))
val frameLenCnt = RegInit(0.U(12.W))
@@ -99,15 +82,12 @@ class SlaveSendGen extends Module with RequireAsyncReset{
}
}
when( stateCurr =/= stateNext ){
lengthCnt := 0.U
} .elsewhen(io.send.fire){
lengthCnt := lengthCnt + 1.U
}
io.frameReq.ready := true.B
io.subMsgHeadReq.ready := stateCurr =/= STATE_SUBMSG_HEADER & stateNext === STATE_SUBMSG_HEADER
io.subMsgTailReq.ready := stateCurr =/= STATE_SUBMSG_TAIL & stateNext === STATE_SUBMSG_TAIL
@@ -137,7 +117,6 @@ class SlaveSendGen extends Module with RequireAsyncReset{
), STATE_SUBMSG_TAIL ),
(stateCurr === STATE_CRC) -> Mux( io.send.fire, Mux( lengthCnt === (4-1).U, STATE_IDLE, STATE_CRC ), STATE_CRC),
// (stateCurr === STATE_ERROR) -> Mux( io.send.fire, STATE_IDLE, STATE_ERROR),
(stateCurr === STATE_WAIT) -> Mux( io.subMsgHeadReq.valid, STATE_SUBMSG_HEADER, STATE_WAIT),
))
)
@@ -149,7 +128,6 @@ class SlaveSendGen extends Module with RequireAsyncReset{
assert( ~(io.data(1).ready & ~io.data(1).valid) )
io.send.valid :=
(stateCurr === STATE_FRAME_HEADER) |
(stateCurr === STATE_SUBMSG_HEADER) |
@@ -157,7 +135,6 @@ class SlaveSendGen extends Module with RequireAsyncReset{
(stateCurr === STATE_SUBMSG_TAIL) |
(stateCurr === STATE_CRC)
val tdata_frame_header = Mux1H(Seq(
(lengthCnt === 0.U) -> frameInfo.frameLenAim(11,4),
(lengthCnt === 1.U) -> Cat( frameInfo.frameLenAim(3,0), 0.U(2.W), frameInfo.frameStyle),
@@ -207,9 +184,7 @@ class SlaveSendGen extends Module with RequireAsyncReset{
(stateCurr === STATE_CRC) -> tdata_crc,
))
io.send.bits.tuser := false.B//(stateCurr === STATE_ERROR & stateNext === STATE_IDLE)
io.send.bits.tlast := (stateCurr === STATE_CRC & stateNext === STATE_IDLE) //|| (stateCurr === STATE_ERROR & stateNext === STATE_IDLE)
io.send.bits.tuser := false.B
io.send.bits.tlast := (stateCurr === STATE_CRC & stateNext === STATE_IDLE)
}

10
src/main/scala/backBoard/shin/SpiInterface.scala
View File

@@ -74,16 +74,6 @@ abstract class SpiInterfaceBase extends Module with RequireAsyncReset{
}
}
class SSpiInterface extends SpiInterfaceBase{

78
src/main/scala/backBoard/shin/b4b5.scala Normal file
View File

@@ -0,0 +1,78 @@
package BACK
import chisel3._
import chisel3.util._
object b4b5Encoder{
def apply( enq: UInt ): UInt = {
Mux1H(Seq(
(enq === "b0000".U) -> "b11110".U(5.W),
(enq === "b0001".U) -> "b01001".U(5.W),
(enq === "b0010".U) -> "b10100".U(5.W),
(enq === "b0011".U) -> "b10101".U(5.W),
(enq === "b0100".U) -> "b01010".U(5.W),
(enq === "b0101".U) -> "b01011".U(5.W),
(enq === "b0110".U) -> "b01110".U(5.W),
(enq === "b0111".U) -> "b01111".U(5.W),
(enq === "b1000".U) -> "b10010".U(5.W),
(enq === "b1001".U) -> "b10011".U(5.W),
(enq === "b1010".U) -> "b10110".U(5.W),
(enq === "b1011".U) -> "b10111".U(5.W),
(enq === "b1100".U) -> "b11010".U(5.W),
(enq === "b1101".U) -> "b11011".U(5.W),
(enq === "b1110".U) -> "b11100".U(5.W),
(enq === "b1111".U) -> "b11101".U(5.W),
))
}
}
object b4b5Decoder{
def apply( enq: UInt ): UInt = {
Mux1H(Seq(
(enq === "b11110".U) -> "b0000".U(4.W),
(enq === "b01001".U) -> "b0001".U(4.W),
(enq === "b10100".U) -> "b0010".U(4.W),
(enq === "b10101".U) -> "b0011".U(4.W),
(enq === "b01010".U) -> "b0100".U(4.W),
(enq === "b01011".U) -> "b0101".U(4.W),
(enq === "b01110".U) -> "b0110".U(4.W),
(enq === "b01111".U) -> "b0111".U(4.W),
(enq === "b10010".U) -> "b1000".U(4.W),
(enq === "b10011".U) -> "b1001".U(4.W),
(enq === "b10110".U) -> "b1010".U(4.W),
(enq === "b10111".U) -> "b1011".U(4.W),
(enq === "b11010".U) -> "b1100".U(4.W),
(enq === "b11011".U) -> "b1101".U(4.W),
(enq === "b11100".U) -> "b1110".U(4.W),
(enq === "b11101".U) -> "b1111".U(4.W),
))
}
}
object Dualb4b5Encoder{
def apply( enq: UInt ): UInt = {
require( enq.getWidth == 8, "Require Failed @ Dualb4b5Encoder!" )
Cat( b4b5Encoder(enq(7,4)), b4b5Encoder(enq(3,0)) )
}
}
object Dualb4b5Decoder{
def apply( enq: UInt ): UInt = {
require( enq.getWidth == 10, "Require Failed @ Dualb4b5Decoder!" )
Cat( b4b5Decoder(enq(9,5)), b4b5Decoder(enq(4,0)) )
}
}
class b4b5DualEncode extends Module with RequireAsyncReset{
val io = IO(new Encode_Bundle)
io.dataOut := Dualb4b5Encoder(io.dataIn)
}
class b4b5DualDecode extends Module with RequireAsyncReset{
val io = IO(new Decode_Bundle)
io.dataOut := Dualb4b5Decoder(io.dataIn)
}

192
src/main/scala/backBoard/shin/b8b10.scala Normal file
View File

@@ -0,0 +1,192 @@
package BACK
import chisel3._
import chisel3.util._
class Encode_Bundle extends Bundle{
val dataIn = Input(UInt(8.W))
val isEnable = Input(Bool())
val dataOut = Output(UInt(10.W))
}
class Decode_Bundle extends Bundle{
val dataIn = Input(UInt(10.W))
val dataOut = Output(UInt(8.W))
}
class b8b10Encode extends Module with RequireAsyncReset{
val io = IO(new Encode_Bundle)
val rdTest = IO(Output(Bool())) //测试使用
dontTouch(rdTest)
val rd = RegInit(false.B); rdTest := rd
val b5b6LookUp = Mux1H(Seq(
(io.dataIn(4,0) === "b00000".U) -> Mux( ~rd, "b100111".U(6.W), "b011000".U(6.W) ),
(io.dataIn(4,0) === "b00001".U) -> Mux( ~rd, "b011101".U(6.W), "b100010".U(6.W) ),
(io.dataIn(4,0) === "b00010".U) -> Mux( ~rd, "b101101".U(6.W), "b010010".U(6.W) ),
(io.dataIn(4,0) === "b00011".U) -> "b110001".U(6.W),
(io.dataIn(4,0) === "b00100".U) -> Mux( ~rd, "b110101".U(6.W), "b001010".U(6.W) ),
(io.dataIn(4,0) === "b00101".U) -> "b101001".U(6.W),
(io.dataIn(4,0) === "b00110".U) -> "b011001".U(6.W),
(io.dataIn(4,0) === "b00111".U) -> Mux( ~rd, "b111000".U(6.W), "b000111".U(6.W) ),
(io.dataIn(4,0) === "b01000".U) -> Mux( ~rd, "b111001".U(6.W), "b000110".U(6.W) ),
(io.dataIn(4,0) === "b01001".U) -> "b100101".U(6.W),
(io.dataIn(4,0) === "b01010".U) -> "b010101".U(6.W),
(io.dataIn(4,0) === "b01011".U) -> "b110100".U(6.W),
(io.dataIn(4,0) === "b01100".U) -> "b001101".U(6.W),
(io.dataIn(4,0) === "b01101".U) -> "b101100".U(6.W),
(io.dataIn(4,0) === "b01110".U) -> "b011100".U(6.W),
(io.dataIn(4,0) === "b01111".U) -> Mux( ~rd, "b010111".U(6.W), "b101000".U(6.W) ),
(io.dataIn(4,0) === "b10000".U) -> Mux( ~rd, "b011011".U(6.W), "b100100".U(6.W) ),
(io.dataIn(4,0) === "b10001".U) -> "b100011".U(6.W),
(io.dataIn(4,0) === "b10010".U) -> "b010011".U(6.W),
(io.dataIn(4,0) === "b10011".U) -> "b110010".U(6.W),
(io.dataIn(4,0) === "b10100".U) -> "b001011".U(6.W),
(io.dataIn(4,0) === "b10101".U) -> "b101010".U(6.W),
(io.dataIn(4,0) === "b10110".U) -> "b011010".U(6.W),
(io.dataIn(4,0) === "b10111".U) -> Mux( ~rd, "b111010".U(6.W), "b000101".U(6.W) ),
(io.dataIn(4,0) === "b11000".U) -> Mux( ~rd, "b110011".U(6.W), "b001100".U(6.W) ),
(io.dataIn(4,0) === "b11001".U) -> "b100110".U(6.W),
(io.dataIn(4,0) === "b11010".U) -> "b010110".U(6.W),
(io.dataIn(4,0) === "b11011".U) -> Mux( ~rd, "b110110".U(6.W), "b001001".U(6.W) ),
(io.dataIn(4,0) === "b11100".U) -> "b001110".U(6.W),
(io.dataIn(4,0) === "b11101".U) -> Mux( ~rd, "b101110".U(6.W), "b010001".U(6.W) ),
(io.dataIn(4,0) === "b11110".U) -> Mux( ~rd, "b011110".U(6.W), "b100001".U(6.W) ),
(io.dataIn(4,0) === "b11111".U) -> Mux( ~rd, "b101011".U(6.W), "b010100".U(6.W) )
))
val b5b6RD = Mux1H(Seq(
(io.dataIn(4,0) === "b00000".U) -> ~rd,
(io.dataIn(4,0) === "b00001".U) -> ~rd,
(io.dataIn(4,0) === "b00010".U) -> ~rd,
(io.dataIn(4,0) === "b00011".U) -> rd,
(io.dataIn(4,0) === "b00100".U) -> ~rd,
(io.dataIn(4,0) === "b00101".U) -> rd,
(io.dataIn(4,0) === "b00110".U) -> rd,
(io.dataIn(4,0) === "b00111".U) -> rd,
(io.dataIn(4,0) === "b01000".U) -> ~rd,
(io.dataIn(4,0) === "b01001".U) -> rd,
(io.dataIn(4,0) === "b01010".U) -> rd,
(io.dataIn(4,0) === "b01011".U) -> rd,
(io.dataIn(4,0) === "b01100".U) -> rd,
(io.dataIn(4,0) === "b01101".U) -> rd,
(io.dataIn(4,0) === "b01110".U) -> rd,
(io.dataIn(4,0) === "b01111".U) -> ~rd,
(io.dataIn(4,0) === "b10000".U) -> ~rd,
(io.dataIn(4,0) === "b10001".U) -> rd,
(io.dataIn(4,0) === "b10010".U) -> rd,
(io.dataIn(4,0) === "b10011".U) -> rd,
(io.dataIn(4,0) === "b10100".U) -> rd,
(io.dataIn(4,0) === "b10101".U) -> rd,
(io.dataIn(4,0) === "b10110".U) -> rd,
(io.dataIn(4,0) === "b10111".U) -> ~rd,
(io.dataIn(4,0) === "b11000".U) -> ~rd,
(io.dataIn(4,0) === "b11001".U) -> rd,
(io.dataIn(4,0) === "b11010".U) -> rd,
(io.dataIn(4,0) === "b11011".U) -> ~rd,
(io.dataIn(4,0) === "b11100".U) -> rd,
(io.dataIn(4,0) === "b11101".U) -> ~rd,
(io.dataIn(4,0) === "b11110".U) -> ~rd,
(io.dataIn(4,0) === "b11111".U) -> ~rd,
))
val b3b4LookUp = Mux1H(Seq(
(io.dataIn(7,5) === "b000".U) -> Mux( ~b5b6RD, "b1011".U(4.W), "b0100".U(4.W) ),
(io.dataIn(7,5) === "b001".U) -> "b1001".U(4.W),
(io.dataIn(7,5) === "b010".U) -> "b0101".U(4.W),
(io.dataIn(7,5) === "b011".U) -> Mux( ~b5b6RD, "b1100".U(4.W), "b0011".U(4.W) ),
(io.dataIn(7,5) === "b100".U) -> Mux( ~b5b6RD, "b1101".U(4.W), "b0010".U(4.W) ),
(io.dataIn(7,5) === "b101".U) -> "b1010".U(4.W),
(io.dataIn(7,5) === "b110".U) -> "b0110".U(4.W),
(io.dataIn(7,5) === "b111".U) -> MuxCase( Mux( ~b5b6RD, "b1110".U(4.W), "b0001".U(4.W) ), Array(
((io.dataIn(4,0) === 17.U || io.dataIn(4,0) === 18.U || io.dataIn(4,0) === 20.U) & ~b5b6RD) -> "b0111".U(4.W), // 17, 18, 20 are special cases
((io.dataIn(4,0) === 11.U || io.dataIn(4,0) === 13.U || io.dataIn(4,0) === 14.U) & b5b6RD) -> "b1000".U(4.W), // 11, 13, 14 are special cases
))
))
val b3b4RD = Mux1H(Seq(
(io.dataIn(7,5) === "b000".U) -> ~b5b6RD,
(io.dataIn(7,5) === "b001".U) -> b5b6RD,
(io.dataIn(7,5) === "b010".U) -> b5b6RD,
(io.dataIn(7,5) === "b011".U) -> b5b6RD,
(io.dataIn(7,5) === "b100".U) -> ~b5b6RD,
(io.dataIn(7,5) === "b101".U) -> b5b6RD,
(io.dataIn(7,5) === "b110".U) -> b5b6RD,
(io.dataIn(7,5) === "b111".U) -> ~b5b6RD,
))
io.dataOut := Cat(b5b6LookUp, b3b4LookUp)
when (io.isEnable) {
rd := b3b4RD
assert( io.dataOut(4,0) =/= 0.U && io.dataOut(4,0) =/= 31.U, "Invalid 8b10b encoding Output!")
assert( io.dataOut(5,1) =/= 0.U && io.dataOut(5,1) =/= 31.U, "Invalid 8b10b encoding Output!")
assert( io.dataOut(6,2) =/= 0.U && io.dataOut(6,2) =/= 31.U, "Invalid 8b10b encoding Output!")
assert( io.dataOut(7,3) =/= 0.U && io.dataOut(7,3) =/= 31.U, "Invalid 8b10b encoding Output!")
assert( io.dataOut(8,4) =/= 0.U && io.dataOut(8,4) =/= 31.U, "Invalid 8b10b encoding Output!")
assert( io.dataOut(9,5) =/= 0.U && io.dataOut(9,5) =/= 31.U, "Invalid 8b10b encoding Output!")
}
}
class b8b10Decode extends Module with RequireAsyncReset{
val io = IO(new Decode_Bundle)
val b5b6LookUp = Mux1H(Seq(
(io.dataIn(9,4) === "b100111".U(6.W) || io.dataIn(9,4) === "b011000".U(6.W) ) -> "b00000".U,
(io.dataIn(9,4) === "b011101".U(6.W) || io.dataIn(9,4) === "b100010".U(6.W) ) -> "b00001".U,
(io.dataIn(9,4) === "b101101".U(6.W) || io.dataIn(9,4) === "b010010".U(6.W) ) -> "b00010".U,
(io.dataIn(9,4) === "b110001".U(6.W)) -> "b00011".U,
(io.dataIn(9,4) === "b110101".U(6.W) || io.dataIn(9,4) === "b001010".U(6.W) ) -> "b00100".U,
(io.dataIn(9,4) === "b101001".U(6.W)) -> "b00101".U,
(io.dataIn(9,4) === "b011001".U(6.W)) -> "b00110".U,
(io.dataIn(9,4) === "b111000".U(6.W) || io.dataIn(9,4) === "b000111".U(6.W) ) -> "b00111".U,
(io.dataIn(9,4) === "b111001".U(6.W) || io.dataIn(9,4) === "b000110".U(6.W) ) -> "b01000".U,
(io.dataIn(9,4) === "b100101".U(6.W)) -> "b01001".U,
(io.dataIn(9,4) === "b010101".U(6.W)) -> "b01010".U,
(io.dataIn(9,4) === "b110100".U(6.W)) -> "b01011".U,
(io.dataIn(9,4) === "b001101".U(6.W)) -> "b01100".U,
(io.dataIn(9,4) === "b101100".U(6.W)) -> "b01101".U,
(io.dataIn(9,4) === "b011100".U(6.W)) -> "b01110".U,
(io.dataIn(9,4) === "b010111".U(6.W) || io.dataIn(9,4) === "b101000".U(6.W) ) -> "b01111".U,
(io.dataIn(9,4) === "b011011".U(6.W) || io.dataIn(9,4) === "b100100".U(6.W) ) -> "b10000".U,
(io.dataIn(9,4) === "b100011".U(6.W)) -> "b10001".U,
(io.dataIn(9,4) === "b010011".U(6.W)) -> "b10010".U,
(io.dataIn(9,4) === "b110010".U(6.W)) -> "b10011".U,
(io.dataIn(9,4) === "b001011".U(6.W)) -> "b10100".U,
(io.dataIn(9,4) === "b101010".U(6.W)) -> "b10101".U,
(io.dataIn(9,4) === "b011010".U(6.W)) -> "b10110".U,
(io.dataIn(9,4) === "b111010".U(6.W) || io.dataIn(9,4) === "b000101".U(6.W) ) -> "b10111".U,
(io.dataIn(9,4) === "b110011".U(6.W) || io.dataIn(9,4) === "b001100".U(6.W) ) -> "b11000".U,
(io.dataIn(9,4) === "b100110".U(6.W)) -> "b11001".U,
(io.dataIn(9,4) === "b010110".U(6.W)) -> "b11010".U,
(io.dataIn(9,4) === "b110110".U(6.W) || io.dataIn(9,4) === "b001001".U(6.W) ) -> "b11011".U,
(io.dataIn(9,4) === "b001110".U(6.W)) -> "b11100".U,
(io.dataIn(9,4) === "b101110".U(6.W) || io.dataIn(9,4) === "b010001".U(6.W) ) -> "b11101".U,
(io.dataIn(9,4) === "b011110".U(6.W) || io.dataIn(9,4) === "b100001".U(6.W) ) -> "b11110".U,
(io.dataIn(9,4) === "b101011".U(6.W) || io.dataIn(9,4) === "b010100".U(6.W) ) -> "b11111".U,
))
val b3b4LookUp = Mux1H(Seq(
(io.dataIn(3,0) === "b1011".U(4.W) || io.dataIn(3,0) === "b0100".U(4.W) ) -> "b000".U,
(io.dataIn(3,0) === "b1001".U(4.W)) -> "b001".U,
(io.dataIn(3,0) === "b0101".U(4.W)) -> "b010".U,
(io.dataIn(3,0) === "b1100".U(4.W) || io.dataIn(3,0) === "b0011".U(4.W) ) -> "b011".U,
(io.dataIn(3,0) === "b1101".U(4.W) || io.dataIn(3,0) === "b0010".U(4.W) ) -> "b100".U,
(io.dataIn(3,0) === "b1010".U(4.W)) -> "b101".U,
(io.dataIn(3,0) === "b0110".U(4.W)) -> "b110".U,
(io.dataIn(3,0) === "b1110".U(4.W) ||
io.dataIn(3,0) === "b0001".U(4.W) ||
io.dataIn(3,0) === "b0111".U(4.W) ||
io.dataIn(3,0) === "b1000".U(4.W)) -> "b111".U,
))
io.dataOut := Cat(b3b4LookUp, b5b6LookUp)
}

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src/main/scala/backBoard/shin/crc32.scala Normal file
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package BACK
import chisel3._
import chisel3.util._
//-----------------------------------------------------------------------------
// Copyright (C) 2009 OutputLogic.com
// This source file may be used and distributed without restriction
// provided that this copyright statement is not removed from the file
// and that any derivative work contains the original copyright notice
// and the associated disclaimer.
//
// THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY EXPRESS
// OR IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
// WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
//-----------------------------------------------------------------------------
// CRC module for data[7:0] , crc[31:0]=1+x^1+x^2+x^4+x^5+x^7+x^8+x^10+x^11+x^12+x^16+x^22+x^23+x^26+x^32;
//-----------------------------------------------------------------------------
class crc32_8() extends Module with RequireAsyncReset{
class crc32IO_Bundle extends Bundle{
val isEnable = Input(Bool())
val dataIn = Input(UInt(8.W))
val crc = Output(UInt(32.W))
val flush = Input(Bool())
}
val io = IO( new crc32IO_Bundle )
// val LFSR_POLY = "h4c11db7".U
val lfsr_c = for( i <- 0 until 32 ) yield Wire(Bool())
val lfsr_q = for( i <- 0 until 32 ) yield RegInit( true.B )
for( i <- 0 until 32 ){
when( io.flush ){
lfsr_q(i) := true.B
} .elsewhen( io.isEnable ){
lfsr_q(i) := lfsr_c(i)
}
}
io.crc := Cat( lfsr_q )
val dataIn = Wire(UInt(8.W))
dataIn := Cat(io.dataIn.asBools)
lfsr_c( 0) := lfsr_q(24) ^ lfsr_q(30) ^ dataIn(0) ^ dataIn(6)
lfsr_c( 1) := lfsr_q(24) ^ lfsr_q(25) ^ lfsr_q(30) ^ lfsr_q(31) ^ dataIn(0) ^ dataIn(1) ^ dataIn(6) ^ dataIn(7)
lfsr_c( 2) := lfsr_q(24) ^ lfsr_q(25) ^ lfsr_q(26) ^ lfsr_q(30) ^ lfsr_q(31) ^ dataIn(0) ^ dataIn(1) ^ dataIn(2) ^ dataIn(6) ^ dataIn(7)
lfsr_c( 3) := lfsr_q(25) ^ lfsr_q(26) ^ lfsr_q(27) ^ lfsr_q(31) ^ dataIn(1) ^ dataIn(2) ^ dataIn(3) ^ dataIn(7)
lfsr_c( 4) := lfsr_q(24) ^ lfsr_q(26) ^ lfsr_q(27) ^ lfsr_q(28) ^ lfsr_q(30) ^ dataIn(0) ^ dataIn(2) ^ dataIn(3) ^ dataIn(4) ^ dataIn(6)
lfsr_c( 5) := lfsr_q(24) ^ lfsr_q(25) ^ lfsr_q(27) ^ lfsr_q(28) ^ lfsr_q(29) ^ lfsr_q(30) ^ lfsr_q(31) ^ dataIn(0) ^ dataIn(1) ^ dataIn(3) ^ dataIn(4) ^ dataIn(5) ^ dataIn(6) ^ dataIn(7)
lfsr_c( 6) := lfsr_q(25) ^ lfsr_q(26) ^ lfsr_q(28) ^ lfsr_q(29) ^ lfsr_q(30) ^ lfsr_q(31) ^ dataIn(1) ^ dataIn(2) ^ dataIn(4) ^ dataIn(5) ^ dataIn(6) ^ dataIn(7)
lfsr_c( 7) := lfsr_q(24) ^ lfsr_q(26) ^ lfsr_q(27) ^ lfsr_q(29) ^ lfsr_q(31) ^ dataIn(0) ^ dataIn(2) ^ dataIn(3) ^ dataIn(5) ^ dataIn(7)
lfsr_c( 8) := lfsr_q( 0) ^ lfsr_q(24) ^ lfsr_q(25) ^ lfsr_q(27) ^ lfsr_q(28) ^ dataIn(0) ^ dataIn(1) ^ dataIn(3) ^ dataIn(4)
lfsr_c( 9) := lfsr_q( 1) ^ lfsr_q(25) ^ lfsr_q(26) ^ lfsr_q(28) ^ lfsr_q(29) ^ dataIn(1) ^ dataIn(2) ^ dataIn(4) ^ dataIn(5)
lfsr_c(10) := lfsr_q( 2) ^ lfsr_q(24) ^ lfsr_q(26) ^ lfsr_q(27) ^ lfsr_q(29) ^ dataIn(0) ^ dataIn(2) ^ dataIn(3) ^ dataIn(5)
lfsr_c(11) := lfsr_q( 3) ^ lfsr_q(24) ^ lfsr_q(25) ^ lfsr_q(27) ^ lfsr_q(28) ^ dataIn(0) ^ dataIn(1) ^ dataIn(3) ^ dataIn(4)
lfsr_c(12) := lfsr_q( 4) ^ lfsr_q(24) ^ lfsr_q(25) ^ lfsr_q(26) ^ lfsr_q(28) ^ lfsr_q(29) ^ lfsr_q(30) ^ dataIn(0) ^ dataIn(1) ^ dataIn(2) ^ dataIn(4) ^ dataIn(5) ^ dataIn(6)
lfsr_c(13) := lfsr_q( 5) ^ lfsr_q(25) ^ lfsr_q(26) ^ lfsr_q(27) ^ lfsr_q(29) ^ lfsr_q(30) ^ lfsr_q(31) ^ dataIn(1) ^ dataIn(2) ^ dataIn(3) ^ dataIn(5) ^ dataIn(6) ^ dataIn(7)
lfsr_c(14) := lfsr_q( 6) ^ lfsr_q(26) ^ lfsr_q(27) ^ lfsr_q(28) ^ lfsr_q(30) ^ lfsr_q(31) ^ dataIn(2) ^ dataIn(3) ^ dataIn(4) ^ dataIn(6) ^ dataIn(7)
lfsr_c(15) := lfsr_q( 7) ^ lfsr_q(27) ^ lfsr_q(28) ^ lfsr_q(29) ^ lfsr_q(31) ^ dataIn(3) ^ dataIn(4) ^ dataIn(5) ^ dataIn(7)
lfsr_c(16) := lfsr_q( 8) ^ lfsr_q(24) ^ lfsr_q(28) ^ lfsr_q(29) ^ dataIn(0) ^ dataIn(4) ^ dataIn(5)
lfsr_c(17) := lfsr_q( 9) ^ lfsr_q(25) ^ lfsr_q(29) ^ lfsr_q(30) ^ dataIn(1) ^ dataIn(5) ^ dataIn(6)
lfsr_c(18) := lfsr_q(10) ^ lfsr_q(26) ^ lfsr_q(30) ^ lfsr_q(31) ^ dataIn(2) ^ dataIn(6) ^ dataIn(7)
lfsr_c(19) := lfsr_q(11) ^ lfsr_q(27) ^ lfsr_q(31) ^ dataIn(3) ^ dataIn(7)
lfsr_c(20) := lfsr_q(12) ^ lfsr_q(28) ^ dataIn(4)
lfsr_c(21) := lfsr_q(13) ^ lfsr_q(29) ^ dataIn(5)
lfsr_c(22) := lfsr_q(14) ^ lfsr_q(24) ^ dataIn(0)
lfsr_c(23) := lfsr_q(15) ^ lfsr_q(24) ^ lfsr_q(25) ^ lfsr_q(30) ^ dataIn(0) ^ dataIn(1) ^ dataIn(6)
lfsr_c(24) := lfsr_q(16) ^ lfsr_q(25) ^ lfsr_q(26) ^ lfsr_q(31) ^ dataIn(1) ^ dataIn(2) ^ dataIn(7)
lfsr_c(25) := lfsr_q(17) ^ lfsr_q(26) ^ lfsr_q(27) ^ dataIn(2) ^ dataIn(3)
lfsr_c(26) := lfsr_q(18) ^ lfsr_q(24) ^ lfsr_q(27) ^ lfsr_q(28) ^ lfsr_q(30) ^ dataIn(0) ^ dataIn(3) ^ dataIn(4) ^ dataIn(6)
lfsr_c(27) := lfsr_q(19) ^ lfsr_q(25) ^ lfsr_q(28) ^ lfsr_q(29) ^ lfsr_q(31) ^ dataIn(1) ^ dataIn(4) ^ dataIn(5) ^ dataIn(7)
lfsr_c(28) := lfsr_q(20) ^ lfsr_q(26) ^ lfsr_q(29) ^ lfsr_q(30) ^ dataIn(2) ^ dataIn(5) ^ dataIn(6)
lfsr_c(29) := lfsr_q(21) ^ lfsr_q(27) ^ lfsr_q(30) ^ lfsr_q(31) ^ dataIn(3) ^ dataIn(6) ^ dataIn(7)
lfsr_c(30) := lfsr_q(22) ^ lfsr_q(28) ^ lfsr_q(31) ^ dataIn(4) ^ dataIn(7)
lfsr_c(31) := lfsr_q(23) ^ lfsr_q(29) ^ dataIn(5)
}