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BUG FIX

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This commit is contained in:
RuigeLee
2023-08-31 15:10:18 +08:00
parent 860e24ca99
commit d226487a5e
2 changed files with 8 additions and 12 deletions
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16
src/main/scala/backBoard/BackBoardMst.scala
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@@ -58,7 +58,7 @@ trait BackBoardMstFSMC{ this: BackBoardMstBase =>
withClockAndReset( io.ides_pclk.asClock, io.reset ){ withClockAndReset( io.ides_pclk.asClock, io.reset ){
val statusReg = RegInit(0.U(8.W)); status := statusReg val statusReg = RegInit(0.U(8.W)); status := statusReg
val slvNumReg = RegInit(31.U(5.W)); slvNum := slvNumReg val slvNumReg = RegInit(1.U(5.W)); slvNum := slvNumReg
val fsmcAddrSync = ShiftRegister( io.FSMC.addr, 2, 0.U, true.B ) val fsmcAddrSync = ShiftRegister( io.FSMC.addr, 2, 0.U, true.B )
val fsmcdataInSync = ShiftRegister( io.FSMC.dataIn, 2, 0.U, true.B ) val fsmcdataInSync = ShiftRegister( io.FSMC.dataIn, 2, 0.U, true.B )
@@ -125,10 +125,6 @@ trait BackBoardMstLVDS{ this: BackBoardMstBase =>
val stateCur = RegInit(3.U(4.W)) val stateCur = RegInit(3.U(4.W))
stateCur_wire := stateCur stateCur_wire := stateCur
// val outOfInit = RegInit(false.B)
// val ( _, init ) = Counter(Range( 0,4096))
// when( init ) { outOfInit := true.B }
val ( _, trigger ) = Counter(Range( 0,2000) ) val ( _, trigger ) = Counter(Range( 0,2000) )
trigger_wire := trigger trigger_wire := trigger
@@ -166,8 +162,8 @@ trait BackBoardMstLVDS{ this: BackBoardMstBase =>
frame_info_update_en := true.B frame_info_update_en := true.B
slave_type_num := Mux(isSync, Cat( "b000".U(3.W), slvNum ), Cat( "b10".U(2.W), 0.U(6.W) ) ) slave_type_num := Mux(isSync, Cat( "b000".U(3.W), slvNum ), Cat( "b100".U(3.W), slvNum ) )
slave_data_length := Mux(isSync, (8/8*4*8-1).U, 0.U ) slave_data_length := (8/8*4*8-1).U
tx_start := false.B tx_start := false.B
} .elsewhen( stateCur === 1.U ){ // tx start } .elsewhen( stateCur === 1.U ){ // tx start
@@ -192,9 +188,9 @@ trait BackBoardMstLVDS{ this: BackBoardMstBase =>
} }
} }
withClockAndReset( io.ides_pclk.asClock, io.reset ){ withClockAndReset( io.oser_pclk.asClock, io.reset ){
val addrr = RegInit(0.U) val addrr = RegInit(0.U(11.W))
val addrw = RegInit(0.U) val addrw = RegInit(0.U(11.W))
when( trigger_wire ){ when( trigger_wire ){
addrw := 0.U addrw := 0.U

4
src/main/scala/backBoard/BackBoardSlv.scala
View File

@@ -62,7 +62,7 @@ abstract class BackBoardSlvBase extends RawModule{
trait BackBoardSlvDown{ this: BackBoardSlvBase => trait BackBoardSlvDown{ this: BackBoardSlvBase =>
withClockAndReset( io.ides_pclk.asClock, io.reset ){ withClockAndReset( io.oser_pclk.asClock, io.reset ){
val downReg = Reg(Vec(32, UInt(8.W))); downRegWire := downReg val downReg = Reg(Vec(32, UInt(8.W))); downRegWire := downReg
@@ -104,7 +104,7 @@ trait BackBoardSlvDown{ this: BackBoardSlvBase =>
trait BackBoardSlvUp{ this: BackBoardSlvBase => trait BackBoardSlvUp{ this: BackBoardSlvBase =>
withClockAndReset( io.ides_pclk.asClock, io.reset ){ withClockAndReset( io.oser_pclk.asClock, io.reset ){
val upCnt = RegInit(0.U(6.W)) val upCnt = RegInit(0.U(6.W))
val upTimeoutEn = RegInit( false.B ) val upTimeoutEn = RegInit( false.B )
val upTimeoutRst = (upCnt === 0.U & lvdsSlv.io.upstream_tx_data_ready) val upTimeoutRst = (upCnt === 0.U & lvdsSlv.io.upstream_tx_data_ready)