From d226487a5e09dfe75fe59b9c7a7fb006655d1ba9 Mon Sep 17 00:00:00 2001 From: RuigeLee Date: Thu, 31 Aug 2023 15:10:18 +0800 Subject: [PATCH] BUG FIX --- src/main/scala/backBoard/BackBoardMst.scala | 16 ++++++---------- src/main/scala/backBoard/BackBoardSlv.scala | 4 ++-- 2 files changed, 8 insertions(+), 12 deletions(-) diff --git a/src/main/scala/backBoard/BackBoardMst.scala b/src/main/scala/backBoard/BackBoardMst.scala index 8360edb..d4f8103 100644 --- a/src/main/scala/backBoard/BackBoardMst.scala +++ b/src/main/scala/backBoard/BackBoardMst.scala @@ -58,7 +58,7 @@ trait BackBoardMstFSMC{ this: BackBoardMstBase => withClockAndReset( io.ides_pclk.asClock, io.reset ){ val statusReg = RegInit(0.U(8.W)); status := statusReg - val slvNumReg = RegInit(31.U(5.W)); slvNum := slvNumReg + val slvNumReg = RegInit(1.U(5.W)); slvNum := slvNumReg val fsmcAddrSync = ShiftRegister( io.FSMC.addr, 2, 0.U, true.B ) val fsmcdataInSync = ShiftRegister( io.FSMC.dataIn, 2, 0.U, true.B ) @@ -125,10 +125,6 @@ trait BackBoardMstLVDS{ this: BackBoardMstBase => val stateCur = RegInit(3.U(4.W)) stateCur_wire := stateCur - // val outOfInit = RegInit(false.B) - - // val ( _, init ) = Counter(Range( 0,4096)) - // when( init ) { outOfInit := true.B } val ( _, trigger ) = Counter(Range( 0,2000) ) trigger_wire := trigger @@ -166,8 +162,8 @@ trait BackBoardMstLVDS{ this: BackBoardMstBase => frame_info_update_en := true.B - slave_type_num := Mux(isSync, Cat( "b000".U(3.W), slvNum ), Cat( "b10".U(2.W), 0.U(6.W) ) ) - slave_data_length := Mux(isSync, (8/8*4*8-1).U, 0.U ) + slave_type_num := Mux(isSync, Cat( "b000".U(3.W), slvNum ), Cat( "b100".U(3.W), slvNum ) ) + slave_data_length := (8/8*4*8-1).U tx_start := false.B } .elsewhen( stateCur === 1.U ){ // tx start @@ -192,9 +188,9 @@ trait BackBoardMstLVDS{ this: BackBoardMstBase => } } - withClockAndReset( io.ides_pclk.asClock, io.reset ){ - val addrr = RegInit(0.U) - val addrw = RegInit(0.U) + withClockAndReset( io.oser_pclk.asClock, io.reset ){ + val addrr = RegInit(0.U(11.W)) + val addrw = RegInit(0.U(11.W)) when( trigger_wire ){ addrw := 0.U diff --git a/src/main/scala/backBoard/BackBoardSlv.scala b/src/main/scala/backBoard/BackBoardSlv.scala index 8c82078..2293abc 100644 --- a/src/main/scala/backBoard/BackBoardSlv.scala +++ b/src/main/scala/backBoard/BackBoardSlv.scala @@ -62,7 +62,7 @@ abstract class BackBoardSlvBase extends RawModule{ trait BackBoardSlvDown{ this: BackBoardSlvBase => - withClockAndReset( io.ides_pclk.asClock, io.reset ){ + withClockAndReset( io.oser_pclk.asClock, io.reset ){ val downReg = Reg(Vec(32, UInt(8.W))); downRegWire := downReg @@ -104,7 +104,7 @@ trait BackBoardSlvDown{ this: BackBoardSlvBase => trait BackBoardSlvUp{ this: BackBoardSlvBase => - withClockAndReset( io.ides_pclk.asClock, io.reset ){ + withClockAndReset( io.oser_pclk.asClock, io.reset ){ val upCnt = RegInit(0.U(6.W)) val upTimeoutEn = RegInit( false.B ) val upTimeoutRst = (upCnt === 0.U & lvdsSlv.io.upstream_tx_data_ready)