ruige/eb001
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

BUG FIX

Browse Source
This commit is contained in:
RuigeLee
2023-08-31 15:10:18 +08:00
parent 860e24ca99
commit d226487a5e
2 changed files with 8 additions and 12 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
src/main/scala/backBoard/BackBoardSlv.scala
View File

@@ -62,7 +62,7 @@ abstract class BackBoardSlvBase extends RawModule{
trait BackBoardSlvDown{ this: BackBoardSlvBase =>
withClockAndReset( io.ides_pclk.asClock, io.reset ){
withClockAndReset( io.oser_pclk.asClock, io.reset ){
val downReg = Reg(Vec(32, UInt(8.W))); downRegWire := downReg
@@ -104,7 +104,7 @@ trait BackBoardSlvDown{ this: BackBoardSlvBase =>
trait BackBoardSlvUp{ this: BackBoardSlvBase =>
withClockAndReset( io.ides_pclk.asClock, io.reset ){
withClockAndReset( io.oser_pclk.asClock, io.reset ){
val upCnt = RegInit(0.U(6.W))
val upTimeoutEn = RegInit( false.B )
val upTimeoutRst = (upCnt === 0.U & lvdsSlv.io.upstream_tx_data_ready)