timing close

2023-08-02 15:17:16 +08:00
parent 5d43600680
commit d09aff40f2
2 changed files with 30 additions and 16 deletions
--- a/src/test/scala/gcd/test.scala
+++ b/src/test/scala/gcd/test.scala
@@ -20,6 +20,10 @@ object testModule extends App {
      ChiselGeneratorAnnotation(() => { new BackBoardSlv })
    ))

+  (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/", "-E", "verilog" ) ++ args, Seq(
+      ChiselGeneratorAnnotation(() => { new BackPlaneMstTest })
+    ))
+
  // val cfg = new MacCfg

  // (new chisel3.stage.ChiselStage).execute( Array("--show-registrations", "--full-stacktrace", "--target-dir", "generated/Main") ++ args, Seq(