From d09aff40f2f1bd259d82c7c27e866ad5d4553f7a Mon Sep 17 00:00:00 2001
From: RuigeLee <wut.ruigeli@gmail.com>
Date: Wed, 2 Aug 2023 15:17:16 +0800
Subject: [PATCH] timing close

---
 src/main/scala/backBoard/CDR4MultiIn.scala | 42 +++++++++++++---------
 src/test/scala/gcd/test.scala              |  4 +++
 2 files changed, 30 insertions(+), 16 deletions(-)

diff --git a/src/main/scala/backBoard/CDR4MultiIn.scala b/src/main/scala/backBoard/CDR4MultiIn.scala
index c0cddf8..33ab0ab 100644
--- a/src/main/scala/backBoard/CDR4MultiIn.scala
+++ b/src/main/scala/backBoard/CDR4MultiIn.scala
@@ -22,15 +22,19 @@ class CDR4MultiInIO() extends Bundle{
 class CDR4MultiIn() extends Module{
   val io: CDR4MultiInIO = IO(new CDR4MultiInIO())
 
-  val inBusToAsync = Wire( new AsyncBundle(new CDRData) )
+  val latValidSet = Wire(Bool())
+
+  val latValidSetAsync = ShiftRegister( latValidSet, 2, false.B, true.B )
+  val latValidReset    = RegNext(latValidSetAsync, false.B)
+
+  val transInfo = Wire(new CDRData)
 
   withClockAndReset( io.clk4.asClock, reset ){
-    val latAValid = RegInit(false.B)
-    val latAInfo = Reg(new CDRData)
-    val shiftDat = RegInit( 0.U( ((1+6+8+32+16)*4+2).W ) )
-    val latAReady = Wire(Bool())
+    val latValidSetReg     = RegInit(false.B); latValidSet := latValidSetReg
+    val latValidResetAsync = ShiftRegister(latValidReset, 2, false.B, true.B)
+
+    val shiftDat = RegInit( 0.U( ((1+6+8+32+16)*4+2).W ) )
 
-    val transInfo = Wire(new CDRData)
 
     transInfo := 
       Cat(
@@ -38,25 +42,31 @@ class CDR4MultiIn() extends Module{
       ).asTypeOf(new CDRData)
 
 
-    when( latAValid & latAReady ){
+    when( latValidSetReg & latValidResetAsync ){
       shiftDat := 0.U
-      latAValid := false.B
+      latValidSetReg := false.B
     } .elsewhen( shiftDat.extract(0) =/= 1.U ){
       shiftDat := Cat(io.dat, shiftDat( ((1+6+8+32+16)*4+2)-1, 1) ) 
     } .elsewhen( shiftDat.extract(0) === 1.U ){
-      latAValid := true.B
-      latAInfo  := transInfo
+      latValidSetReg := true.B
     }
 
-    val inBusASyncIO  = Wire( new DecoupledIO(new CDRData) )
-    inBusASyncIO.valid := latAValid
-    inBusASyncIO.bits  := latAInfo
-    latAReady := inBusASyncIO.ready
-    inBusToAsync <> ToAsyncBundle( inBusASyncIO, AsyncQueueParams(sync=2) )
+
   }
 
+  val latDatValid = RegInit(false.B)
+  val latDatInfo  = Reg(new CDRData)
+
+  when( io.latDat.fire ){
+    latDatValid := false.B
+  } .elsewhen( latValidSetAsync & ~latValidReset){
+    latDatValid := true.B
+    latDatInfo  := transInfo
+  }
+
+  io.latDat.valid := latDatValid
+  io.latDat.bits  := latDatInfo
 
-    io.latDat <> FromAsyncBundle( inBusToAsync, 2 )
 
 }
 
diff --git a/src/test/scala/gcd/test.scala b/src/test/scala/gcd/test.scala
index 20245e3..ce59a30 100644
--- a/src/test/scala/gcd/test.scala
+++ b/src/test/scala/gcd/test.scala
@@ -20,6 +20,10 @@ object testModule extends App {
       ChiselGeneratorAnnotation(() => { new BackBoardSlv })
     ))
 
+  (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/", "-E", "verilog" ) ++ args, Seq(
+      ChiselGeneratorAnnotation(() => { new BackPlaneMstTest })
+    ))
+
   // val cfg = new MacCfg
 
   // (new chisel3.stage.ChiselStage).execute( Array("--show-registrations", "--full-stacktrace", "--target-dir", "generated/Main") ++ args, Seq(