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寄存器空间优化

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This commit is contained in:
RuigeLee
2024-05-21 19:37:00 +08:00
parent 35281910b4
commit cf76ef1595
1 changed files with 42 additions and 35 deletions
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77
src/main/scala/backBoard/BackBoardMst.scala
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@@ -61,6 +61,21 @@ class BackBoardMstIO extends Bundle{
} }
class BackBoardMstBase extends Module{ //10M class BackBoardMstBase extends Module{ //10M
def OPERATORADDR = 0.U
def STATUSINITADDR = 1.U
def STATUSSYNCHADDR = 2.U
def STATUSTRANSADDR = 3.U
def STATUSUNICASTADDR = 4.U
def SLVNUMADDR = 5.U
def SLVDATALENADDR = 6.U
def SLVLINKNUMADDR = 7.U
def LINKERRLOCADDR = 8.U
def STATUSLINKERRADDR = 9.U
def STATUSCDRERRADDR = 10.U
def STATUSCRCERRADDR = 11.U
val io: BackBoardMstIO = IO(new BackBoardMstIO) val io: BackBoardMstIO = IO(new BackBoardMstIO)
val mirrorDown = Module(new MirrorSRAMDP()) val mirrorDown = Module(new MirrorSRAMDP())
@@ -144,7 +159,7 @@ trait BackBoardMstFSMC{ this: BackBoardMstBase =>
val testIOShift = ShiftRegisters(io.testIO, 3, false.B, true.B) val testIOShift = ShiftRegisters(io.testIO, 3, false.B, true.B)
when(~testIOShift(0) & io.testIO){ when(~testIOShift(0) & io.testIO){
mirrorReg.io.addrB := 1.U mirrorReg.io.addrB := OPERATORADDR
mirrorReg.io.enrB := true.B mirrorReg.io.enrB := true.B
} .elsewhen( ~testIOShift(1) & testIOShift(0)){ } .elsewhen( ~testIOShift(1) & testIOShift(0)){
when( mirrorReg.io.datarB === 0.U ){ when( mirrorReg.io.datarB === 0.U ){
@@ -204,14 +219,14 @@ trait BackBoardMstLVDSInit{ this: BackBoardMstLVDSBase =>
stateCur := 1.U stateCur := 1.U
// write statusInit // write statusInit
mirrorReg.io.addrB := 7.U mirrorReg.io.addrB := STATUSINITADDR
mirrorReg.io.datawB := 0.U mirrorReg.io.datawB := 0.U
mirrorReg.io.enwB := true.B mirrorReg.io.enwB := true.B
} .elsewhen( stateCur === 1.U ){ } .elsewhen( stateCur === 1.U ){
stateCur := 2.U stateCur := 2.U
//req slvnum //req slvnum
mirrorReg.io.addrB := 2.U mirrorReg.io.addrB := SLVNUMADDR
mirrorReg.io.enrB := true.B mirrorReg.io.enrB := true.B
} .elsewhen( stateCur === 2.U ){ } .elsewhen( stateCur === 2.U ){
@@ -221,7 +236,7 @@ trait BackBoardMstLVDSInit{ this: BackBoardMstLVDSBase =>
slvNum := mirrorReg.io.datarB slvNum := mirrorReg.io.datarB
//req slaveDataLength //req slaveDataLength
mirrorReg.io.addrB := 6.U mirrorReg.io.addrB := SLVDATALENADDR
mirrorReg.io.enrB := true.B mirrorReg.io.enrB := true.B
} }
@@ -233,7 +248,6 @@ trait BackBoardMstLVDSInit{ this: BackBoardMstLVDSBase =>
frame_info_update_en := true.B frame_info_update_en := true.B
slave_type_num := Cat( "b00".U(2.W), slvNum ) slave_type_num := Cat( "b00".U(2.W), slvNum )
// slaveDataLength := slaveDataLength
tx_start := false.B tx_start := false.B
} .elsewhen( stateCur === 4.U ){ // tx start } .elsewhen( stateCur === 4.U ){ // tx start
@@ -251,7 +265,7 @@ trait BackBoardMstLVDSInit{ this: BackBoardMstLVDSBase =>
stateCur := 6.U stateCur := 6.U
//linkNum //linkNum
mirrorReg.io.addrB := 5.U mirrorReg.io.addrB := SLVLINKNUMADDR
mirrorReg.io.datawB := io.lvdsMst.slave_link_num mirrorReg.io.datawB := io.lvdsMst.slave_link_num
mirrorReg.io.enwB := true.B mirrorReg.io.enwB := true.B
@@ -261,7 +275,7 @@ trait BackBoardMstLVDSInit{ this: BackBoardMstLVDSBase =>
stateCur := 6.U stateCur := 6.U
//linkNum //linkNum
mirrorReg.io.addrB := 5.U mirrorReg.io.addrB := SLVLINKNUMADDR
mirrorReg.io.datawB := 0.U mirrorReg.io.datawB := 0.U
mirrorReg.io.enwB := true.B mirrorReg.io.enwB := true.B
@@ -273,7 +287,7 @@ trait BackBoardMstLVDSInit{ this: BackBoardMstLVDSBase =>
stateCur := 7.U stateCur := 7.U
//statusInit //statusInit
mirrorReg.io.addrB := 7.U mirrorReg.io.addrB := STATUSINITADDR
mirrorReg.io.datawB := 1.U mirrorReg.io.datawB := 1.U
mirrorReg.io.enwB := true.B mirrorReg.io.enwB := true.B
@@ -299,14 +313,14 @@ trait BackBoardMstLVDSSync{ this: BackBoardMstLVDSBase =>
} .elsewhen( stateCur === 0.U ){ //statusSynch } .elsewhen( stateCur === 0.U ){ //statusSynch
stateCur := 1.U stateCur := 1.U
mirrorReg.io.addrB := 8.U mirrorReg.io.addrB := STATUSSYNCHADDR
mirrorReg.io.datawB := 0.U mirrorReg.io.datawB := 0.U
mirrorReg.io.enwB := true.B mirrorReg.io.enwB := true.B
} .elsewhen( stateCur === 1.U ){ } .elsewhen( stateCur === 1.U ){
stateCur := 2.U stateCur := 2.U
//req slvnum //req slvnum
mirrorReg.io.addrB := 2.U mirrorReg.io.addrB := SLVNUMADDR
mirrorReg.io.enrB := true.B mirrorReg.io.enrB := true.B
@@ -316,7 +330,8 @@ trait BackBoardMstLVDSSync{ this: BackBoardMstLVDSBase =>
//lock slvNum //lock slvNum
slvNum := mirrorReg.io.datarB slvNum := mirrorReg.io.datarB
mirrorReg.io.addrB := 6.U //slaveDataLength
mirrorReg.io.addrB := SLVDATALENADDR
mirrorReg.io.enrB := true.B mirrorReg.io.enrB := true.B
@@ -328,7 +343,6 @@ trait BackBoardMstLVDSSync{ this: BackBoardMstLVDSBase =>
frame_info_update_en := true.B frame_info_update_en := true.B
slave_type_num := Cat( "b01".U(2.W), slvNum ) slave_type_num := Cat( "b01".U(2.W), slvNum )
// slaveDataLength := slaveDataLength
tx_start := false.B tx_start := false.B
} .elsewhen( stateCur === 4.U ){ // tx start } .elsewhen( stateCur === 4.U ){ // tx start
@@ -345,7 +359,7 @@ trait BackBoardMstLVDSSync{ this: BackBoardMstLVDSBase =>
stateCur := 6.U stateCur := 6.U
//statusSync //statusSync
mirrorReg.io.addrB := 8.U mirrorReg.io.addrB := STATUSSYNCHADDR
mirrorReg.io.datawB := 1.U mirrorReg.io.datawB := 1.U
mirrorReg.io.enwB := true.B mirrorReg.io.enwB := true.B
@@ -378,13 +392,13 @@ trait BackBoardMstLVDSTransmit{ this: BackBoardMstLVDSBase =>
} .elsewhen( stateCur === 0.U ){ //statusTransmit } .elsewhen( stateCur === 0.U ){ //statusTransmit
stateCur := 1.U stateCur := 1.U
mirrorReg.io.addrB := 9.U mirrorReg.io.addrB := STATUSTRANSADDR
mirrorReg.io.datawB := 0.U mirrorReg.io.datawB := 0.U
mirrorReg.io.enwB := true.B mirrorReg.io.enwB := true.B
} .elsewhen( stateCur === 1.U ){ //slvnum } .elsewhen( stateCur === 1.U ){ //slvnum
stateCur := 2.U stateCur := 2.U
mirrorReg.io.addrB := 2.U mirrorReg.io.addrB := SLVNUMADDR
mirrorReg.io.enrB := true.B mirrorReg.io.enrB := true.B
} .elsewhen( stateCur === 2.U ){ //slaveDataLength } .elsewhen( stateCur === 2.U ){ //slaveDataLength
@@ -393,7 +407,7 @@ trait BackBoardMstLVDSTransmit{ this: BackBoardMstLVDSBase =>
//lock slvNum //lock slvNum
slvNum := mirrorReg.io.datarB slvNum := mirrorReg.io.datarB
mirrorReg.io.addrB := 6.U mirrorReg.io.addrB := SLVDATALENADDR
mirrorReg.io.enrB := true.B mirrorReg.io.enrB := true.B
} .elsewhen( stateCur === 3.U ){ //setting } .elsewhen( stateCur === 3.U ){ //setting
@@ -404,7 +418,6 @@ trait BackBoardMstLVDSTransmit{ this: BackBoardMstLVDSBase =>
frame_info_update_en := true.B frame_info_update_en := true.B
slave_type_num := Cat( "b10".U(2.W), slvNum ) slave_type_num := Cat( "b10".U(2.W), slvNum )
// slaveDataLength := slaveDataLength
tx_start := false.B tx_start := false.B
} .elsewhen( stateCur === 4.U ){ // tx start } .elsewhen( stateCur === 4.U ){ // tx start
@@ -426,7 +439,7 @@ trait BackBoardMstLVDSTransmit{ this: BackBoardMstLVDSBase =>
stateCur := 7.U stateCur := 7.U
//statusTransmit //statusTransmit
mirrorReg.io.addrB := 9.U mirrorReg.io.addrB := STATUSTRANSADDR
mirrorReg.io.datawB := 1.U mirrorReg.io.datawB := 1.U
mirrorReg.io.enwB := true.B mirrorReg.io.enwB := true.B
@@ -464,13 +477,13 @@ trait BackBoardMstLVDSUnicast{ this: BackBoardMstLVDSBase =>
} .elsewhen( stateCur === 0.U ){ //statusUnicast } .elsewhen( stateCur === 0.U ){ //statusUnicast
stateCur := 1.U stateCur := 1.U
mirrorReg.io.addrB := 13.U mirrorReg.io.addrB := STATUSUNICASTADDR
mirrorReg.io.datawB := 0.U mirrorReg.io.datawB := 0.U
mirrorReg.io.enwB := true.B mirrorReg.io.enwB := true.B
} .elsewhen( stateCur === 1.U ){ //slvnum } .elsewhen( stateCur === 1.U ){ //slvnum
stateCur := 2.U stateCur := 2.U
mirrorReg.io.addrB := 2.U mirrorReg.io.addrB := SLVNUMADDR
mirrorReg.io.enrB := true.B mirrorReg.io.enrB := true.B
} .elsewhen( stateCur === 2.U ){ //slaveDataLength } .elsewhen( stateCur === 2.U ){ //slaveDataLength
@@ -479,7 +492,7 @@ trait BackBoardMstLVDSUnicast{ this: BackBoardMstLVDSBase =>
//lock slvNum //lock slvNum
slvNum := mirrorReg.io.datarB slvNum := mirrorReg.io.datarB
mirrorReg.io.addrB := 6.U mirrorReg.io.addrB := SLVDATALENADDR
mirrorReg.io.enrB := true.B mirrorReg.io.enrB := true.B
} .elsewhen( stateCur === 3.U ){ //setting } .elsewhen( stateCur === 3.U ){ //setting
@@ -490,7 +503,6 @@ trait BackBoardMstLVDSUnicast{ this: BackBoardMstLVDSBase =>
frame_info_update_en := true.B frame_info_update_en := true.B
slave_type_num := Cat( "b11".U(2.W), slvNum ) slave_type_num := Cat( "b11".U(2.W), slvNum )
// slaveDataLength := slaveDataLength
tx_start := false.B tx_start := false.B
} .elsewhen( stateCur === 4.U ){ // tx start } .elsewhen( stateCur === 4.U ){ // tx start
@@ -512,7 +524,7 @@ trait BackBoardMstLVDSUnicast{ this: BackBoardMstLVDSBase =>
stateCur := 7.U stateCur := 7.U
//statusUnicast //statusUnicast
mirrorReg.io.addrB := 13.U mirrorReg.io.addrB := STATUSUNICASTADDR
mirrorReg.io.datawB := 1.U mirrorReg.io.datawB := 1.U
mirrorReg.io.enwB := true.B mirrorReg.io.enwB := true.B
@@ -534,34 +546,31 @@ trait BackBoardMstLVDSUnicast{ this: BackBoardMstLVDSBase =>
trait BackBoardMstLVDSError{ this: BackBoardMstLVDSBase => trait BackBoardMstLVDSError{ this: BackBoardMstLVDSBase =>
val shiftClosedLoopErr = ShiftRegisters( io.lvdsMst.closed_loop_err, 6, false.B, true.B ) val shiftClosedLoopErr = ShiftRegisters( io.lvdsMst.closed_loop_err, 6, false.B, true.B )
when( ~shiftClosedLoopErr(0) & io.lvdsMst.closed_loop_err ){ when( ~shiftClosedLoopErr(0) & io.lvdsMst.closed_loop_err ){
mirrorReg.io.addrB := LINKERRLOCADDR
//slvOffLine := io.lvdsMst.link_err_location(5,0)
mirrorReg.io.addrB := 3.U
mirrorReg.io.datawB := io.lvdsMst.link_err_location(5,0) mirrorReg.io.datawB := io.lvdsMst.link_err_location(5,0)
mirrorReg.io.enwB := true.B mirrorReg.io.enwB := true.B
} .elsewhen( ~shiftClosedLoopErr(1) & shiftClosedLoopErr(0) ){ } .elsewhen( ~shiftClosedLoopErr(1) & shiftClosedLoopErr(0) ){
//statusLinkErr := true.B mirrorReg.io.addrB := STATUSLINKERRADDR
mirrorReg.io.addrB := 10.U
mirrorReg.io.datawB := 1.U mirrorReg.io.datawB := 1.U
mirrorReg.io.enwB := true.B mirrorReg.io.enwB := true.B
} .elsewhen( ~shiftClosedLoopErr(2) & shiftClosedLoopErr(1) ){ } .elsewhen( ~shiftClosedLoopErr(2) & shiftClosedLoopErr(1) ){
mirrorReg.io.addrB := 8.U mirrorReg.io.addrB := STATUSSYNCHADDR
mirrorReg.io.datawB := 1.U mirrorReg.io.datawB := 1.U
mirrorReg.io.enwB := true.B mirrorReg.io.enwB := true.B
ctrlSynch := false.B ctrlSynch := false.B
} .elsewhen( ~shiftClosedLoopErr(3) & shiftClosedLoopErr(2) ){ } .elsewhen( ~shiftClosedLoopErr(3) & shiftClosedLoopErr(2) ){
mirrorReg.io.addrB := 9.U mirrorReg.io.addrB := STATUSTRANSADDR
mirrorReg.io.datawB := 1.U mirrorReg.io.datawB := 1.U
mirrorReg.io.enwB := true.B mirrorReg.io.enwB := true.B
ctrlTransmit := false.B ctrlTransmit := false.B
} .elsewhen( ~shiftClosedLoopErr(4) & shiftClosedLoopErr(3) ){ } .elsewhen( ~shiftClosedLoopErr(4) & shiftClosedLoopErr(3) ){
mirrorReg.io.addrB := 13.U mirrorReg.io.addrB := STATUSUNICASTADDR
mirrorReg.io.datawB := 1.U mirrorReg.io.datawB := 1.U
mirrorReg.io.enwB := true.B mirrorReg.io.enwB := true.B
@@ -574,16 +583,14 @@ trait BackBoardMstLVDSError{ this: BackBoardMstLVDSBase =>
when( io.lvdsMst.upstream_cdr_err ){ when( io.lvdsMst.upstream_cdr_err ){
// statusCDRErr := true.B mirrorReg.io.addrB := STATUSCDRERRADDR
mirrorReg.io.addrB := 11.U
mirrorReg.io.datawB := 1.U mirrorReg.io.datawB := 1.U
mirrorReg.io.enwB := true.B mirrorReg.io.enwB := true.B
interrupt := true.B interrupt := true.B
} }
when( io.lvdsMst.upstream_crc_valid & io.lvdsMst.upstream_crc_err ){ when( io.lvdsMst.upstream_crc_valid & io.lvdsMst.upstream_crc_err ){
// statusCRCErr := true.B mirrorReg.io.addrB := STATUSCRCERRADDR
mirrorReg.io.addrB := 12.U
mirrorReg.io.datawB := 1.U mirrorReg.io.datawB := 1.U
mirrorReg.io.enwB := true.B mirrorReg.io.enwB := true.B
interrupt := true.B interrupt := true.B