diff --git a/src/main/scala/backBoard/BackBoardMst.scala b/src/main/scala/backBoard/BackBoardMst.scala
index c0283ed..5c481f4 100644
--- a/src/main/scala/backBoard/BackBoardMst.scala
+++ b/src/main/scala/backBoard/BackBoardMst.scala
@@ -61,6 +61,21 @@ class BackBoardMstIO extends Bundle{
 }
 
 class BackBoardMstBase extends Module{ //10M
+
+  def OPERATORADDR      = 0.U
+  def STATUSINITADDR    = 1.U
+  def STATUSSYNCHADDR   = 2.U
+  def STATUSTRANSADDR   = 3.U
+  def STATUSUNICASTADDR = 4.U
+  def SLVNUMADDR        = 5.U
+  def SLVDATALENADDR    = 6.U
+  def SLVLINKNUMADDR    = 7.U
+  def LINKERRLOCADDR    = 8.U
+  def STATUSLINKERRADDR = 9.U
+  def STATUSCDRERRADDR  = 10.U
+  def STATUSCRCERRADDR  = 11.U
+
+
   val io: BackBoardMstIO = IO(new BackBoardMstIO)
 
   val mirrorDown = Module(new MirrorSRAMDP())
@@ -144,7 +159,7 @@ trait BackBoardMstFSMC{ this: BackBoardMstBase =>
   val testIOShift = ShiftRegisters(io.testIO, 3, false.B, true.B)
   when(~testIOShift(0) & io.testIO){
 
-    mirrorReg.io.addrB  := 1.U
+    mirrorReg.io.addrB  := OPERATORADDR
     mirrorReg.io.enrB   := true.B
   } .elsewhen( ~testIOShift(1) & testIOShift(0)){
     when( mirrorReg.io.datarB === 0.U ){
@@ -204,14 +219,14 @@ trait BackBoardMstLVDSInit{ this: BackBoardMstLVDSBase =>
       stateCur := 1.U
 
       // write statusInit
-      mirrorReg.io.addrB  := 7.U
+      mirrorReg.io.addrB  := STATUSINITADDR
       mirrorReg.io.datawB := 0.U
       mirrorReg.io.enwB   := true.B
     } .elsewhen( stateCur === 1.U ){
       stateCur := 2.U
 
       //req slvnum
-      mirrorReg.io.addrB := 2.U
+      mirrorReg.io.addrB := SLVNUMADDR
       mirrorReg.io.enrB  := true.B
 
     } .elsewhen( stateCur === 2.U ){
@@ -221,7 +236,7 @@ trait BackBoardMstLVDSInit{ this: BackBoardMstLVDSBase =>
       slvNum := mirrorReg.io.datarB
 
       //req slaveDataLength
-      mirrorReg.io.addrB  := 6.U
+      mirrorReg.io.addrB  := SLVDATALENADDR
       mirrorReg.io.enrB  := true.B
 
     }
@@ -233,7 +248,6 @@ trait BackBoardMstLVDSInit{ this: BackBoardMstLVDSBase =>
 
       frame_info_update_en := true.B
       slave_type_num       := Cat( "b00".U(2.W), slvNum )
-      // slaveDataLength      := slaveDataLength
 
       tx_start := false.B
     } .elsewhen( stateCur === 4.U ){ // tx start
@@ -251,7 +265,7 @@ trait BackBoardMstLVDSInit{ this: BackBoardMstLVDSBase =>
         stateCur := 6.U
 
         //linkNum 
-        mirrorReg.io.addrB  := 5.U
+        mirrorReg.io.addrB  := SLVLINKNUMADDR
         mirrorReg.io.datawB := io.lvdsMst.slave_link_num
         mirrorReg.io.enwB   := true.B
 
@@ -261,7 +275,7 @@ trait BackBoardMstLVDSInit{ this: BackBoardMstLVDSBase =>
         stateCur := 6.U
 
         //linkNum 
-        mirrorReg.io.addrB  := 5.U
+        mirrorReg.io.addrB  := SLVLINKNUMADDR
         mirrorReg.io.datawB := 0.U
         mirrorReg.io.enwB   := true.B
 
@@ -273,7 +287,7 @@ trait BackBoardMstLVDSInit{ this: BackBoardMstLVDSBase =>
       stateCur := 7.U
 
       //statusInit 
-      mirrorReg.io.addrB  := 7.U
+      mirrorReg.io.addrB  := STATUSINITADDR
       mirrorReg.io.datawB := 1.U
       mirrorReg.io.enwB   := true.B
 
@@ -299,14 +313,14 @@ trait BackBoardMstLVDSSync{ this: BackBoardMstLVDSBase =>
     } .elsewhen( stateCur === 0.U ){ //statusSynch
       stateCur := 1.U
 
-      mirrorReg.io.addrB  := 8.U
+      mirrorReg.io.addrB  := STATUSSYNCHADDR
       mirrorReg.io.datawB := 0.U
       mirrorReg.io.enwB   := true.B
     } .elsewhen( stateCur === 1.U ){ 
       stateCur := 2.U
 
       //req slvnum
-      mirrorReg.io.addrB  := 2.U
+      mirrorReg.io.addrB  := SLVNUMADDR
       mirrorReg.io.enrB   := true.B
 
 
@@ -316,7 +330,8 @@ trait BackBoardMstLVDSSync{ this: BackBoardMstLVDSBase =>
       //lock slvNum
       slvNum := mirrorReg.io.datarB
 
-      mirrorReg.io.addrB  := 6.U
+      //slaveDataLength
+      mirrorReg.io.addrB  := SLVDATALENADDR
       mirrorReg.io.enrB   := true.B
 
 
@@ -328,7 +343,6 @@ trait BackBoardMstLVDSSync{ this: BackBoardMstLVDSBase =>
 
       frame_info_update_en := true.B
       slave_type_num       := Cat( "b01".U(2.W), slvNum )
-      // slaveDataLength      := slaveDataLength
 
       tx_start := false.B
     } .elsewhen( stateCur === 4.U ){ // tx start
@@ -345,7 +359,7 @@ trait BackBoardMstLVDSSync{ this: BackBoardMstLVDSBase =>
         stateCur := 6.U
 
         //statusSync
-        mirrorReg.io.addrB  := 8.U
+        mirrorReg.io.addrB  := STATUSSYNCHADDR
         mirrorReg.io.datawB := 1.U
         mirrorReg.io.enwB   := true.B
 
@@ -378,13 +392,13 @@ trait BackBoardMstLVDSTransmit{ this: BackBoardMstLVDSBase =>
     }  .elsewhen( stateCur === 0.U ){ //statusTransmit
       stateCur := 1.U
 
-      mirrorReg.io.addrB  := 9.U
+      mirrorReg.io.addrB  := STATUSTRANSADDR
       mirrorReg.io.datawB := 0.U
       mirrorReg.io.enwB   := true.B
     } .elsewhen( stateCur === 1.U ){ //slvnum
       stateCur := 2.U
 
-      mirrorReg.io.addrB  := 2.U
+      mirrorReg.io.addrB  := SLVNUMADDR
       mirrorReg.io.enrB   := true.B
 
     } .elsewhen( stateCur === 2.U ){ //slaveDataLength
@@ -393,7 +407,7 @@ trait BackBoardMstLVDSTransmit{ this: BackBoardMstLVDSBase =>
       //lock slvNum
       slvNum := mirrorReg.io.datarB
 
-      mirrorReg.io.addrB  := 6.U
+      mirrorReg.io.addrB  := SLVDATALENADDR
       mirrorReg.io.enrB   := true.B
 
     } .elsewhen( stateCur === 3.U  ){ //setting
@@ -404,7 +418,6 @@ trait BackBoardMstLVDSTransmit{ this: BackBoardMstLVDSBase =>
 
       frame_info_update_en := true.B
       slave_type_num       := Cat( "b10".U(2.W), slvNum )
-      // slaveDataLength      := slaveDataLength
 
       tx_start := false.B
     } .elsewhen( stateCur === 4.U ){ // tx start
@@ -426,7 +439,7 @@ trait BackBoardMstLVDSTransmit{ this: BackBoardMstLVDSBase =>
         stateCur := 7.U
 
         //statusTransmit
-        mirrorReg.io.addrB  := 9.U
+        mirrorReg.io.addrB  := STATUSTRANSADDR
         mirrorReg.io.datawB := 1.U
         mirrorReg.io.enwB   := true.B
 
@@ -464,13 +477,13 @@ trait BackBoardMstLVDSUnicast{ this: BackBoardMstLVDSBase =>
     }  .elsewhen( stateCur === 0.U ){ //statusUnicast
       stateCur := 1.U
 
-      mirrorReg.io.addrB  := 13.U
+      mirrorReg.io.addrB  := STATUSUNICASTADDR
       mirrorReg.io.datawB := 0.U
       mirrorReg.io.enwB   := true.B
     } .elsewhen( stateCur === 1.U ){ //slvnum
       stateCur := 2.U
 
-      mirrorReg.io.addrB  := 2.U
+      mirrorReg.io.addrB  := SLVNUMADDR
       mirrorReg.io.enrB   := true.B
 
     } .elsewhen( stateCur === 2.U ){ //slaveDataLength
@@ -479,7 +492,7 @@ trait BackBoardMstLVDSUnicast{ this: BackBoardMstLVDSBase =>
       //lock slvNum
       slvNum := mirrorReg.io.datarB
 
-      mirrorReg.io.addrB  := 6.U
+      mirrorReg.io.addrB  := SLVDATALENADDR
       mirrorReg.io.enrB   := true.B
 
     } .elsewhen( stateCur === 3.U  ){ //setting
@@ -490,7 +503,6 @@ trait BackBoardMstLVDSUnicast{ this: BackBoardMstLVDSBase =>
 
       frame_info_update_en := true.B
       slave_type_num       := Cat( "b11".U(2.W), slvNum )
-      // slaveDataLength      := slaveDataLength
 
       tx_start := false.B
     } .elsewhen( stateCur === 4.U ){ // tx start
@@ -512,7 +524,7 @@ trait BackBoardMstLVDSUnicast{ this: BackBoardMstLVDSBase =>
         stateCur := 7.U
 
         //statusUnicast
-        mirrorReg.io.addrB  := 13.U
+        mirrorReg.io.addrB  := STATUSUNICASTADDR
         mirrorReg.io.datawB := 1.U
         mirrorReg.io.enwB   := true.B
 
@@ -534,34 +546,31 @@ trait BackBoardMstLVDSUnicast{ this: BackBoardMstLVDSBase =>
 trait BackBoardMstLVDSError{ this: BackBoardMstLVDSBase =>
   val shiftClosedLoopErr = ShiftRegisters( io.lvdsMst.closed_loop_err, 6, false.B, true.B )
   when( ~shiftClosedLoopErr(0) & io.lvdsMst.closed_loop_err ){
-
-    //slvOffLine    := io.lvdsMst.link_err_location(5,0)
-    mirrorReg.io.addrB  := 3.U
+    mirrorReg.io.addrB  := LINKERRLOCADDR
     mirrorReg.io.datawB := io.lvdsMst.link_err_location(5,0)
     mirrorReg.io.enwB   := true.B
 
   } .elsewhen( ~shiftClosedLoopErr(1) & shiftClosedLoopErr(0) ){
-    //statusLinkErr := true.B
-    mirrorReg.io.addrB  := 10.U
+    mirrorReg.io.addrB  := STATUSLINKERRADDR
     mirrorReg.io.datawB := 1.U
     mirrorReg.io.enwB   := true.B
 
   } .elsewhen( ~shiftClosedLoopErr(2) & shiftClosedLoopErr(1) ){
-    mirrorReg.io.addrB  := 8.U
+    mirrorReg.io.addrB  := STATUSSYNCHADDR
     mirrorReg.io.datawB := 1.U
     mirrorReg.io.enwB   := true.B
 
     ctrlSynch   := false.B
 
   } .elsewhen( ~shiftClosedLoopErr(3) & shiftClosedLoopErr(2) ){
-    mirrorReg.io.addrB  := 9.U
+    mirrorReg.io.addrB  := STATUSTRANSADDR
     mirrorReg.io.datawB := 1.U
     mirrorReg.io.enwB   := true.B
 
     ctrlTransmit := false.B
 
   } .elsewhen( ~shiftClosedLoopErr(4) & shiftClosedLoopErr(3) ){
-    mirrorReg.io.addrB  := 13.U
+    mirrorReg.io.addrB  := STATUSUNICASTADDR
     mirrorReg.io.datawB := 1.U
     mirrorReg.io.enwB   := true.B
 
@@ -574,16 +583,14 @@ trait BackBoardMstLVDSError{ this: BackBoardMstLVDSBase =>
 
 
   when( io.lvdsMst.upstream_cdr_err ){
-    // statusCDRErr := true.B
-    mirrorReg.io.addrB  := 11.U
+    mirrorReg.io.addrB  := STATUSCDRERRADDR
     mirrorReg.io.datawB := 1.U
     mirrorReg.io.enwB   := true.B   
     interrupt     := true.B
   }
 
   when( io.lvdsMst.upstream_crc_valid & io.lvdsMst.upstream_crc_err ){
-    // statusCRCErr := true.B
-    mirrorReg.io.addrB  := 12.U
+    mirrorReg.io.addrB  := STATUSCRCERRADDR
     mirrorReg.io.datawB := 1.U
     mirrorReg.io.enwB   := true.B   
     interrupt     := true.B