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使用rec的清中断复位sendGen模块；当CDRout的axis下溢，状态机回到IDLE

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This commit is contained in:
Ruige Lee
2025-07-15 16:30:44 +08:00
parent 7b18543883
commit cea2d01945
2 changed files with 13 additions and 5 deletions
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13
src/main/scala/backBoard/ebus/CDROut.scala
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@@ -45,8 +45,8 @@ class CDROut extends Module{
stateNext := Mux1H(Seq( stateNext := Mux1H(Seq(
(stateCurr === STATE_IDLE) -> ( Mux( io.axis.valid, STATE_PREAMBLE, STATE_IDLE )), (stateCurr === STATE_IDLE) -> ( Mux( io.axis.valid, STATE_PREAMBLE, STATE_IDLE )),
(stateCurr === STATE_PREAMBLE) -> ( Mux( (byteCnt === 7.U) & (bitCnt === 9.U), STATE_PAYLOAD, STATE_PREAMBLE )), (stateCurr === STATE_PREAMBLE) -> ( Mux( (byteCnt === 7.U) & (bitCnt === 9.U), Mux( io.axis.valid, STATE_PAYLOAD, STATE_IDLE), STATE_PREAMBLE )),
(stateCurr === STATE_PAYLOAD) -> ( Mux( io.axis.fire & io.axis.bits.tlast, STATE_IDLE, STATE_PAYLOAD ) ), (stateCurr === STATE_PAYLOAD) -> ( Mux( (io.axis.fire & io.axis.bits.tlast) | (~io.axis.valid & io.axis.ready), STATE_IDLE, STATE_PAYLOAD ) ),
)) ))
io.serDat := shiftData.extract(9) io.serDat := shiftData.extract(9)
@@ -62,9 +62,12 @@ class CDROut extends Module{
} }
when( stateCurr === STATE_IDLE ){
when( stateCurr === STATE_IDLE & stateNext === STATE_PREAMBLE){ //PRE when( stateNext === STATE_PREAMBLE ){
shiftData := ETH_PRE shiftData := ETH_PRE
} .elsewhen( stateNext === STATE_IDLE ){
shiftData := 0.U
}
} .otherwise{ } .otherwise{
when( bitCnt =/= 9.U ){ when( bitCnt =/= 9.U ){
shiftData := shiftData << 1 shiftData := shiftData << 1

5
src/main/scala/backBoard/shin/SlaveParser.scala
View File

@@ -1048,7 +1048,12 @@ with SlaveParserProbe{
io.intHWTrig(1) := upRecParser.io.isError io.intHWTrig(1) := upRecParser.io.isError
downRecParser.io.resp := io.intHWClr(0) downRecParser.io.resp := io.intHWClr(0)
downSendGen.reset := reset.asBool | io.intHWClr(0)
upRecParser.io.resp := io.intHWClr(1) upRecParser.io.resp := io.intHWClr(1)
upSendGen.reset := reset.asBool | io.intHWClr(1)
} }