diff --git a/src/main/scala/backBoard/ebus/CDROut.scala b/src/main/scala/backBoard/ebus/CDROut.scala
index 53ccdf0..363183d 100644
--- a/src/main/scala/backBoard/ebus/CDROut.scala
+++ b/src/main/scala/backBoard/ebus/CDROut.scala
@@ -45,8 +45,8 @@ class CDROut extends Module{
 
   stateNext := Mux1H(Seq(
     (stateCurr === STATE_IDLE)     -> ( Mux( io.axis.valid, STATE_PREAMBLE, STATE_IDLE )),
-    (stateCurr === STATE_PREAMBLE) -> ( Mux( (byteCnt === 7.U) & (bitCnt === 9.U), STATE_PAYLOAD, STATE_PREAMBLE )),
-    (stateCurr === STATE_PAYLOAD)  -> ( Mux( io.axis.fire & io.axis.bits.tlast, STATE_IDLE, STATE_PAYLOAD ) ),
+    (stateCurr === STATE_PREAMBLE) -> ( Mux( (byteCnt === 7.U) & (bitCnt === 9.U), Mux( io.axis.valid, STATE_PAYLOAD, STATE_IDLE), STATE_PREAMBLE )),
+    (stateCurr === STATE_PAYLOAD)  -> ( Mux( (io.axis.fire & io.axis.bits.tlast) | (~io.axis.valid & io.axis.ready), STATE_IDLE, STATE_PAYLOAD ) ),
   ))
 
   io.serDat := shiftData.extract(9)
@@ -62,9 +62,12 @@ class CDROut extends Module{
   }
 
 
-
-  when( stateCurr === STATE_IDLE & stateNext === STATE_PREAMBLE){ //PRE
-    shiftData := ETH_PRE
+  when( stateCurr === STATE_IDLE ){
+    when( stateNext === STATE_PREAMBLE ){
+      shiftData := ETH_PRE
+    } .elsewhen( stateNext === STATE_IDLE ){
+      shiftData := 0.U
+    }
   } .otherwise{
     when( bitCnt =/= 9.U ){
       shiftData := shiftData << 1
diff --git a/src/main/scala/backBoard/shin/SlaveParser.scala b/src/main/scala/backBoard/shin/SlaveParser.scala
index d91c21e..df3fd46 100644
--- a/src/main/scala/backBoard/shin/SlaveParser.scala
+++ b/src/main/scala/backBoard/shin/SlaveParser.scala
@@ -1048,7 +1048,12 @@ with SlaveParserProbe{
   io.intHWTrig(1) := upRecParser.io.isError
 
   downRecParser.io.resp := io.intHWClr(0)
+
+  downSendGen.reset   := reset.asBool | io.intHWClr(0)
+
   upRecParser.io.resp   := io.intHWClr(1)
+  upSendGen.reset     := reset.asBool | io.intHWClr(1)
+
 }