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延迟addrr和addrw跳变，尝试突破1：3频率

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This commit is contained in:
Ruige Lee
2025-10-02 13:27:12 +08:00
parent 21bc57e9a7
commit cc0c5a886a
1 changed files with 4 additions and 4 deletions
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8
src/main/scala/backBoard/shin/NSpiInterface.scala
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@@ -93,9 +93,9 @@ trait SyncSpiAsync{ this: SyncSpiInterfaceBase =>
}
when( isEnW_async(0) ){
when( isEnW_async(1) ){
addrw_async(0) := addrw_async(0) + 2.U
} .elsewhen( isEnW_async(1) ){
} .elsewhen( isEnW_async(0) & byteSel >= 7.U ){
addrw_async(1) := addrw_async(1) + 2.U
} .elsewhen( bitSel === 0.U ){
when( byteSel === 1.U ){
@@ -108,9 +108,9 @@ trait SyncSpiAsync{ this: SyncSpiInterfaceBase =>
}
when( isEnR_async(0) ){
when( isEnR_async(1) ){
addrr_async(0) := addrr_async(0) + 2.U
} .elsewhen( isEnR_async(1) ){
} .elsewhen( isEnR_async(0) & byteSel >= 4.U ){
addrr_async(1) := addrr_async(1) + 2.U
} .elsewhen( bitSel === 0.U ){
when( byteSel === 1.U ){