diff --git a/src/main/scala/backBoard/shin/NSpiInterface.scala b/src/main/scala/backBoard/shin/NSpiInterface.scala
index fa347e4..30b6068 100644
--- a/src/main/scala/backBoard/shin/NSpiInterface.scala
+++ b/src/main/scala/backBoard/shin/NSpiInterface.scala
@@ -93,9 +93,9 @@ trait SyncSpiAsync{ this: SyncSpiInterfaceBase =>
   }
 
 
-  when( isEnW_async(0) ){
+  when( isEnW_async(1) ){ 
     addrw_async(0) := addrw_async(0) + 2.U
-  } .elsewhen( isEnW_async(1) ){
+  } .elsewhen( isEnW_async(0) & byteSel >= 7.U  ){
     addrw_async(1) := addrw_async(1) + 2.U
   } .elsewhen( bitSel === 0.U ){
     when( byteSel === 1.U ){
@@ -108,9 +108,9 @@ trait SyncSpiAsync{ this: SyncSpiInterfaceBase =>
   } 
 
 
-  when( isEnR_async(0) ){
+  when( isEnR_async(1) ){
     addrr_async(0) := addrr_async(0) + 2.U
-  } .elsewhen( isEnR_async(1) ){
+  } .elsewhen( isEnR_async(0) & byteSel >= 4.U ){
       addrr_async(1) := addrr_async(1) + 2.U        
   } .elsewhen( bitSel === 0.U ){
     when( byteSel === 1.U ){