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移动smEnq/Deq addr寄存器，合并为len，删除txlength寄存器

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This commit is contained in:
Ruige Lee
2025-05-20 11:32:03 +08:00
parent 090a10ff17
commit cb30c29e07
5 changed files with 110 additions and 126 deletions
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35
src/main/scala/backBoard/shin/MasterParser.scala
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@@ -10,12 +10,9 @@ class MasterParserIO extends Bundle{
val sram_w = Flipped(new SRAM2kWRIO)
val sram_r = Flipped(new SRAM2kRDIO)
val req = Flipped(Valid(new Bundle{
val txLength = UInt(12.W)
}))
val req = Input(Bool())
val rsp = Valid(new Bundle{
val isError = Bool()
val length = UInt(12.W)
})
val rxEnq = Output( Bool())
@@ -50,27 +47,37 @@ abstract class MasterParserBase extends Module{
// io.req.ready := reqReady
when( io.req.fire ){
when( io.req ){
reqReady := false.B
} .elsewhen( io.downOut.fire & txCnt === txLen + (4-1).U ){
reqReady := true.B
}
when( io.req.fire ){
txLen := io.req.bits.txLength
rxLen := io.req.bits.txLength
when( io.req ){
txLen := Mux1H(Seq(
( io.mReg.txSM === 0.U ) -> io.cReg.smTrigLen(1),
( io.mReg.txSM === 1.U ) -> io.cReg.smTrigLen(3),
( io.mReg.txSM === 2.U ) -> io.cReg.smTrigLen(5),
( io.mReg.txSM === 3.U ) -> io.cReg.smTrigLen(7),
))
rxLen := Mux1H(Seq(
( io.mReg.rxSM === 0.U ) -> io.cReg.smTrigLen(0),
( io.mReg.rxSM === 1.U ) -> io.cReg.smTrigLen(2),
( io.mReg.rxSM === 2.U ) -> io.cReg.smTrigLen(4),
( io.mReg.rxSM === 3.U ) -> io.cReg.smTrigLen(6),
))
txCnt := 0.U
} .elsewhen( io.downOut.fire ){
txCnt := txCnt + 1.U
}
when( io.req.fire ){
when( io.req ){
txAddr := 0.U
} .elsewhen( io.downOut.fire ){
txAddr := txAddr + 1.U
}
when( io.req.fire ){
when( io.req ){
rxAddr := 0.U
} .elsewhen( io.upIn.fire ){
rxAddr := rxAddr + 1.U
@@ -79,9 +86,9 @@ abstract class MasterParserBase extends Module{
io.sram_r.enr :=
io.req.fire | io.downOut.fire
io.req | io.downOut.fire
io.sram_r.addrr := Mux( io.req.fire, 0.U, txAddr + 1.U )
io.sram_r.addrr := Mux( io.req, 0.U, txAddr + 1.U )
io.downOut.valid := ~reqReady
@@ -130,7 +137,7 @@ abstract class MasterParserBase extends Module{
val recCrcCheck = Reg(UInt(32.W))
when( io.req.fire ){
when( io.req ){
rxCnt := 0.U
} .elsewhen( io.upIn.fire ){
rxCnt := rxCnt + 1.U
@@ -146,7 +153,7 @@ abstract class MasterParserBase extends Module{
io.rsp.valid := io.upIn.fire & io.upIn.bits.tlast
io.rsp.bits.isError := io.upIn.fire & io.upIn.bits.tlast & recCrcCheck =/= rxcrc.io.crc
io.rsp.bits.length := rxCnt + 1.U
// io.rsp.bits.length := rxCnt + 1.U