diff --git a/src/main/scala/backBoard/shin/Interface.scala b/src/main/scala/backBoard/shin/Interface.scala
index 4f9b865..9678ca9 100644
--- a/src/main/scala/backBoard/shin/Interface.scala
+++ b/src/main/scala/backBoard/shin/Interface.scala
@@ -39,9 +39,9 @@ class CommonRegisterBundle extends Bundle{
   val syncPeroid = UInt(32.W)
 
 
-  val smEnqAddr = Vec(8, UInt(11.W)) //触发SM切换缓冲区的地址 （或读或写）
-  val smDeqAddr = Vec(8, UInt(11.W)) //触发SM切换缓冲区的地址 （或读或写）
-
+  // val smEnqAddr = Vec(8, UInt(11.W)) //触发SM切换缓冲区的地址 （或读或写）
+  // val smDeqAddr = Vec(8, UInt(11.W)) //触发SM切换缓冲区的地址 （或读或写）
+  val smTrigLen = Vec(8, UInt(11.W))  //触发SM切换缓冲区的地址 （或读或写）
 
 
 }
@@ -51,7 +51,7 @@ class MasterRegisterBundle extends Bundle{
 
   val txSM         = UInt(2.W)
   val rxSM         = UInt(2.W)
-  val txLength     = UInt(12.W)
+  // val txLength     = UInt(12.W)
   // val txStatus     = UInt(16.W)
 
   val rplTimeStampTx = UInt(16.W)
@@ -156,7 +156,7 @@ class InterfaceIO extends Bundle{
   val txReq = Valid(new Bundle{
     val txSM = UInt(2.W)
     val rxSM = UInt(2.W)
-    val txLength = UInt(12.W)
+    // val txLength = UInt(12.W)
   }) //发送请求和SM代号
 
 
@@ -182,9 +182,6 @@ class InterfaceIO extends Bundle{
 
 
 
-  // val smEnqAddr = Output(Vec(8, UInt(16.W))) //触发SM切换缓冲区的地址 （或读或写）
-  // val smDeqAddr = Output(Vec(8, UInt(16.W))) //触发SM切换缓冲区的地址 （或读或写）
-  // val mstTimeStamp  = Input(UInt(64.W)) //主站时间戳
   val slvDeltaTime  = Input(UInt(32.W)) //从站时间戳差值
   val mstDeltaTime  = Input(UInt(32.W))
   val deltaFinal = Input(UInt(32.W))
@@ -249,7 +246,7 @@ abstract class InterfaceBase extends Module{
 
 
         (addr === "h20".U & isMstMode) -> Cat(mReg.rxSM, mReg.txSM, 0.U(1.W) ),
-                (addr === "h21".U & isMstMode) -> mReg.txLength,
+                //(addr === "h21".U & isMstMode) -> mReg.txLength,
 
         (addr === "h24".U & isMstMode) -> mReg.rplTimeStampTx(7,0),
         (addr === "h25".U & isMstMode) -> mReg.rplTimeStampTx(15,8),
@@ -357,9 +354,18 @@ abstract class InterfaceBase extends Module{
         (addr === "h145".U & isSlvMode)  -> sReg.syncOffset(3)(15,8),
         (addr === "h146".U & isSlvMode)  -> sReg.syncOffset(3)(23,16),
         (addr === "h147".U & isSlvMode)  -> sReg.syncOffset(3)(31,24),
-      )
+      ) ++
 
+      ( 0 until 8 ).map{ i =>
+        ( addr === ("h302".U + (i*4).U) )  -> cReg.smTrigLen(i)(7,0)
+      } ++
+      ( 0 until 8 ).map{ i =>
+        ( addr === ("h303".U + (i*4).U) )  -> cReg.smTrigLen(i)(10,8)
+      } ++
+      Seq()
     )
+
+
   }
 
 
@@ -455,7 +461,7 @@ trait InterfaceMCUop{ this: InterfaceBase =>
 
   mReg.txSM     := RegEnable( dataw(2,1), 0.U, isEnW & addrSel === "h20".U )
   mReg.rxSM     := RegEnable( dataw(4,3), 0.U, isEnW & addrSel === "h20".U )
-  mReg.txLength := Cat( RegEnable( dataw, 0.U, isEnW & addrSel === "h22".U ), RegEnable( dataw, 0.U, isEnW & addrSel === "h21".U ) )
+  // mReg.txLength := Cat( RegEnable( dataw, 0.U, isEnW & addrSel === "h22".U ), RegEnable( dataw, 0.U, isEnW & addrSel === "h21".U ) )
 
   mReg.rplTimeStampTx := 
     Cat(
@@ -529,16 +535,12 @@ trait InterfaceCheckSM{ this: InterfaceBase =>
   val isEnR: Bool
 
   for( i <- 0 until 8 ){
-    cReg.smEnqAddr(i) := 
+    cReg.smTrigLen(i) := 
       Cat(
-        RegEnable( dataw, 0.U, isEnW & addrSel === ("h201".U + (i*2).U) ),
-        RegEnable( dataw, 0.U, isEnW & addrSel === ("h200".U + (i*2).U) ),
-      )
-    cReg.smDeqAddr(i) := 
-      Cat(
-        RegEnable( dataw, 0.U, isEnW & addrSel === ("h301".U + (i*2).U) ),
-        RegEnable( dataw, 0.U, isEnW & addrSel === ("h300".U + (i*2).U) ),
+        RegEnable( dataw, 0.U, isEnW & addrSel === ("h303".U + (i*4).U) ),
+        RegEnable( dataw, 0.U, isEnW & addrSel === ("h302".U + (i*4).U) ),
       )
+
   }
 
 
@@ -567,15 +569,15 @@ trait InterfaceCheckSM{ this: InterfaceBase =>
   io.sram_w(2).enw   := isEnW & (( addrSel & "hF800".U ) === "h3000".U)
   io.sram_w(3).enw   := isEnW & (( addrSel & "hF800".U ) === "h4000".U)
 
-  io.dSMdeq(0) := isEnR & (( addrSel & "hF800".U ) === "h0800".U) & (addrSel(10,0) === cReg.smDeqAddr(0))
-  io.dSMdeq(1) := isEnR & (( addrSel & "hF800".U ) === "h0800".U) & (addrSel(10,0) === cReg.smDeqAddr(2))
-  io.dSMdeq(2) := isEnR & (( addrSel & "hF800".U ) === "h0800".U) & (addrSel(10,0) === cReg.smDeqAddr(4))
-  io.dSMdeq(3) := isEnR & (( addrSel & "hF800".U ) === "h0800".U) & (addrSel(10,0) === cReg.smDeqAddr(6))
+  io.dSMdeq(0) := isEnR & (( addrSel & "hF800".U ) === "h0800".U) & (addrSel(10,0) === cReg.smTrigLen(0) - 1.U)
+  io.dSMdeq(1) := isEnR & (( addrSel & "hF800".U ) === "h0800".U) & (addrSel(10,0) === cReg.smTrigLen(2) - 1.U)
+  io.dSMdeq(2) := isEnR & (( addrSel & "hF800".U ) === "h0800".U) & (addrSel(10,0) === cReg.smTrigLen(4) - 1.U)
+  io.dSMdeq(3) := isEnR & (( addrSel & "hF800".U ) === "h0800".U) & (addrSel(10,0) === cReg.smTrigLen(6) - 1.U)
 
-  io.uSMenq(0) := isEnW & (( addrSel & "hF800".U ) === "h1000".U) & (addrSel(10,0) === cReg.smEnqAddr(1))
-  io.uSMenq(1) := isEnW & (( addrSel & "hF800".U ) === "h2000".U) & (addrSel(10,0) === cReg.smEnqAddr(3))
-  io.uSMenq(2) := isEnW & (( addrSel & "hF800".U ) === "h3000".U) & (addrSel(10,0) === cReg.smEnqAddr(5))
-  io.uSMenq(3) := isEnW & (( addrSel & "hF800".U ) === "h4000".U) & (addrSel(10,0) === cReg.smEnqAddr(7))
+  io.uSMenq(0) := isEnW & (( addrSel & "hF800".U ) === "h1000".U) & (addrSel(10,0) === cReg.smTrigLen(1) - 1.U)
+  io.uSMenq(1) := isEnW & (( addrSel & "hF800".U ) === "h2000".U) & (addrSel(10,0) === cReg.smTrigLen(3) - 1.U)
+  io.uSMenq(2) := isEnW & (( addrSel & "hF800".U ) === "h3000".U) & (addrSel(10,0) === cReg.smTrigLen(5) - 1.U)
+  io.uSMenq(3) := isEnW & (( addrSel & "hF800".U ) === "h4000".U) & (addrSel(10,0) === cReg.smTrigLen(7) - 1.U)
 }
 
 trait InterfaceLVDSop{ this: InterfaceBase =>
@@ -723,11 +725,10 @@ with InterfaceSync
 
   io.txReq.bits.txSM  := mReg.txSM
   io.txReq.bits.rxSM  := mReg.rxSM
-  io.txReq.bits.txLength := mReg.txLength
+  // io.txReq.bits.txLength := //mReg.txLength
   io.txReq.valid := isEnW & addrSel === "h20".U & dataw.extract(0) === "b1".U //& mReg.txLength =/= 0.U
 
-  // io.smEnqAddr := cReg.smEnqAddr
-  // io.smDeqAddr := cReg.smDeqAddr
+
 
 
   sReg.localDevIndex := io.localDevIndex
diff --git a/src/main/scala/backBoard/shin/MasterParser.scala b/src/main/scala/backBoard/shin/MasterParser.scala
index 3d8b1b2..6f4fe88 100644
--- a/src/main/scala/backBoard/shin/MasterParser.scala
+++ b/src/main/scala/backBoard/shin/MasterParser.scala
@@ -10,12 +10,9 @@ class MasterParserIO extends Bundle{
   val sram_w = Flipped(new SRAM2kWRIO)
   val sram_r = Flipped(new SRAM2kRDIO)
 
-  val req = Flipped(Valid(new Bundle{
-    val txLength  = UInt(12.W)
-  }))
+  val req = Input(Bool())
   val rsp = Valid(new Bundle{
     val isError = Bool()
-    val length  = UInt(12.W)
   })
 
   val rxEnq = Output( Bool())
@@ -50,27 +47,37 @@ abstract class MasterParserBase extends Module{
 
   // io.req.ready := reqReady
 
-  when( io.req.fire ){
+  when( io.req ){
     reqReady := false.B
   } .elsewhen( io.downOut.fire & txCnt === txLen + (4-1).U ){
     reqReady := true.B
   }
 
-  when( io.req.fire ){
-    txLen  := io.req.bits.txLength
-    rxLen  := io.req.bits.txLength
+  when( io.req ){
+    txLen := Mux1H(Seq(
+      ( io.mReg.txSM === 0.U ) -> io.cReg.smTrigLen(1),
+      ( io.mReg.txSM === 1.U ) -> io.cReg.smTrigLen(3),
+      ( io.mReg.txSM === 2.U ) -> io.cReg.smTrigLen(5),
+      ( io.mReg.txSM === 3.U ) -> io.cReg.smTrigLen(7),
+    ))
+    rxLen := Mux1H(Seq(
+      ( io.mReg.rxSM === 0.U ) -> io.cReg.smTrigLen(0),
+      ( io.mReg.rxSM === 1.U ) -> io.cReg.smTrigLen(2),
+      ( io.mReg.rxSM === 2.U ) -> io.cReg.smTrigLen(4),
+      ( io.mReg.rxSM === 3.U ) -> io.cReg.smTrigLen(6),
+    ))
     txCnt  := 0.U
   } .elsewhen( io.downOut.fire ){
     txCnt := txCnt + 1.U
   }
 
-  when( io.req.fire ){
+  when( io.req ){
     txAddr := 0.U
   } .elsewhen( io.downOut.fire ){
     txAddr := txAddr + 1.U
   }
 
-  when( io.req.fire ){
+  when( io.req ){
     rxAddr := 0.U
   } .elsewhen( io.upIn.fire ){
     rxAddr := rxAddr + 1.U
@@ -79,9 +86,9 @@ abstract class MasterParserBase extends Module{
 
 
   io.sram_r.enr := 
-    io.req.fire | io.downOut.fire
+    io.req | io.downOut.fire
 
-  io.sram_r.addrr := Mux( io.req.fire, 0.U, txAddr + 1.U )
+  io.sram_r.addrr := Mux( io.req, 0.U, txAddr + 1.U )
 
   io.downOut.valid := ~reqReady
 
@@ -130,7 +137,7 @@ abstract class MasterParserBase extends Module{
 
   val recCrcCheck = Reg(UInt(32.W))
 
-  when( io.req.fire ){
+  when( io.req ){
     rxCnt := 0.U
   } .elsewhen( io.upIn.fire ){
     rxCnt := rxCnt + 1.U
@@ -146,7 +153,7 @@ abstract class MasterParserBase extends Module{
 
   io.rsp.valid := io.upIn.fire & io.upIn.bits.tlast
   io.rsp.bits.isError := io.upIn.fire & io.upIn.bits.tlast & recCrcCheck =/= rxcrc.io.crc
-  io.rsp.bits.length  := rxCnt + 1.U
+  // io.rsp.bits.length  := rxCnt + 1.U
 
 
 
diff --git a/src/main/scala/backBoard/shin/ShinTop.scala b/src/main/scala/backBoard/shin/ShinTop.scala
index 317ff0f..fd75bb4 100644
--- a/src/main/scala/backBoard/shin/ShinTop.scala
+++ b/src/main/scala/backBoard/shin/ShinTop.scala
@@ -38,7 +38,7 @@ class ShinTopIO extends Bundle{
 
   val rsp = Valid(new Bundle{
     val isError = Bool()
-    val length  = UInt(12.W)
+    // val length  = UInt(12.W)
   })
 
   val iSync = Output(Vec(4, Bool()))
@@ -268,21 +268,13 @@ trait ShinTopMaster{ this: ShinTopBase =>
       smUnit(7).io.deq    := masterParser.io.txDeq
     }
 
-    // _ := interface.io.smEnqAddr(0)
-    // _ := interface.io.smDeqAddr(1)
-    // _ := interface.io.smEnqAddr(2)
-    // _ := interface.io.smDeqAddr(3)
-    // _ := interface.io.smEnqAddr(4)
-    // _ := interface.io.smDeqAddr(5)
-    // _ := interface.io.smEnqAddr(6)
-    // _ := interface.io.smDeqAddr(7)
 
 
     interface.io.mstDeltaTime := masterParser.io.deltaTimeStamp
   }
 
-  masterParser.io.req.valid         := interface.io.txReq.valid
-  masterParser.io.req.bits.txLength := interface.io.txReq.bits.txLength
+  masterParser.io.req         := interface.io.txReq.valid
+  // masterParser.io.req.bits.txLength := interface.io.txReq.bits.txLength
 
   io.rsp := masterParser.io.rsp
 
@@ -305,20 +297,6 @@ trait ShinTopSlave{ this: ShinTopBase =>
   slaveParser.io.cReg := interface.io.cReg
 
 
-
-  slaveParser.io.trigAddr(0) := interface.io.cReg.smEnqAddr(0)
-  slaveParser.io.trigAddr(1) := interface.io.cReg.smDeqAddr(1)
-  slaveParser.io.trigAddr(2) := interface.io.cReg.smEnqAddr(2)
-  slaveParser.io.trigAddr(3) := interface.io.cReg.smDeqAddr(3)
-  slaveParser.io.trigAddr(4) := interface.io.cReg.smEnqAddr(4)
-  slaveParser.io.trigAddr(5) := interface.io.cReg.smDeqAddr(5)
-  slaveParser.io.trigAddr(6) := interface.io.cReg.smEnqAddr(6)
-  slaveParser.io.trigAddr(7) := interface.io.cReg.smDeqAddr(7)
-
-
-
-
-
   when( interface.io.cReg.modeSel === false.B ){
     smUnit(0).io.sram_w := slaveParser.io.sram_w(0)
     smUnit(2).io.sram_w := slaveParser.io.sram_w(1)
diff --git a/src/main/scala/backBoard/shin/SlaveParser.scala b/src/main/scala/backBoard/shin/SlaveParser.scala
index 6232f43..64ac8b1 100644
--- a/src/main/scala/backBoard/shin/SlaveParser.scala
+++ b/src/main/scala/backBoard/shin/SlaveParser.scala
@@ -44,7 +44,7 @@ class SlaveParserIO extends Bundle{
   val dSMenq = Output( Vec(4, Bool()) )
   val uSMdeq = Output( Vec(4, Bool()) )
 
-  val trigAddr = Input( Vec(8, UInt(15.W)) )
+
 
 
   val localDevIndex = Output(UInt(16.W))
@@ -564,14 +564,14 @@ trait SlaveParserRW{ this: SlaveParserBase =>
   io.sram_r(3).addrr := readSMAddr(10,0)
 
 
-  io.dSMenq(0) := isWrite & isWRSM0 & io.trigAddr(0) === addrw(10,0)
-  io.uSMdeq(0) := isRead  & isRDSM1 & io.trigAddr(1) === readSMAddr(10,0)
-  io.dSMenq(1) := isWrite & isWRSM2 & io.trigAddr(2) === addrw(10,0)
-  io.uSMdeq(1) := isRead  & isRDSM3 & io.trigAddr(3) === readSMAddr(10,0)
-  io.dSMenq(2) := isWrite & isWRSM4 & io.trigAddr(4) === addrw(10,0)
-  io.uSMdeq(2) := isRead  & isRDSM5 & io.trigAddr(5) === readSMAddr(10,0)
-  io.dSMenq(3) := isWrite & isWRSM6 & io.trigAddr(6) === addrw(10,0)
-  io.uSMdeq(3) := isRead  & isRDSM7 & io.trigAddr(7) === readSMAddr(10,0)
+  io.dSMenq(0) := isWrite & isWRSM0 & (io.cReg.smTrigLen(0) - 1.U) === addrw(10,0)
+  io.uSMdeq(0) := isRead  & isRDSM1 & (io.cReg.smTrigLen(1) - 1.U) === readSMAddr(10,0)
+  io.dSMenq(1) := isWrite & isWRSM2 & (io.cReg.smTrigLen(2) - 1.U) === addrw(10,0)
+  io.uSMdeq(1) := isRead  & isRDSM3 & (io.cReg.smTrigLen(3) - 1.U) === readSMAddr(10,0)
+  io.dSMenq(2) := isWrite & isWRSM4 & (io.cReg.smTrigLen(4) - 1.U) === addrw(10,0)
+  io.uSMdeq(2) := isRead  & isRDSM5 & (io.cReg.smTrigLen(5) - 1.U) === readSMAddr(10,0)
+  io.dSMenq(3) := isWrite & isWRSM6 & (io.cReg.smTrigLen(6) - 1.U) === addrw(10,0)
+  io.uSMdeq(3) := isRead  & isRDSM7 & (io.cReg.smTrigLen(7) - 1.U) === readSMAddr(10,0)
 
 
 }
diff --git a/tb/shinTest/ShinTopSpiTb.v b/tb/shinTest/ShinTopSpiTb.v
index 7618223..3ac2143 100644
--- a/tb/shinTest/ShinTopSpiTb.v
+++ b/tb/shinTest/ShinTopSpiTb.v
@@ -55,8 +55,8 @@ ShinTop s_ShinTop_Mst(
   .io_oqspi_csn(spi_csn[10]),
 
   .io_rsp_valid(isResp),
-  .io_rsp_bits_isError(),
-  .io_rsp_bits_length()
+  .io_rsp_bits_isError()
+  // .io_rsp_bits_length()
 );
 
 ShinTop s_ShinTop_slv0(
@@ -87,8 +87,8 @@ ShinTop s_ShinTop_slv0(
   .io_oqspi_csn(spi_csn[11]),
 
   .io_rsp_valid(),
-  .io_rsp_bits_isError(),
-  .io_rsp_bits_length()
+  .io_rsp_bits_isError()
+  // .io_rsp_bits_length()
 );
 
 ShinTop s_ShinTop_slv1(
@@ -119,8 +119,8 @@ ShinTop s_ShinTop_slv1(
   .io_oqspi_csn(spi_csn[12]),
 
   .io_rsp_valid(),
-  .io_rsp_bits_isError(),
-  .io_rsp_bits_length()
+  .io_rsp_bits_isError()
+  // .io_rsp_bits_length()
 );
 
 ShinTop s_ShinTop_slv2(
@@ -151,8 +151,8 @@ ShinTop s_ShinTop_slv2(
   .io_oqspi_csn(spi_csn[13]),
 
   .io_rsp_valid(),
-  .io_rsp_bits_isError(),
-  .io_rsp_bits_length()
+  .io_rsp_bits_isError()
+  // .io_rsp_bits_length()
 );
 
 ShinTop s_ShinTop_slv3(
@@ -183,8 +183,8 @@ ShinTop s_ShinTop_slv3(
   .io_oqspi_csn(spi_csn[14]),
 
   .io_rsp_valid(),
-  .io_rsp_bits_isError(),
-  .io_rsp_bits_length()
+  .io_rsp_bits_isError()
+  // .io_rsp_bits_length()
 );
 
 
@@ -506,10 +506,12 @@ initial begin
     spi_trans( (16'h00c0), (`SPI_READ), (6), (`IF_IDX(4)) );
 
     $fdisplay(spidata_file, "--->>>嗅探");
-    //设置SM1在写入0x3地址触发enq
-    txBuf[0+3] = 8'h03;
+    //设置SM1在写入0x4 len 触发enq
+    //设置SM0在读出0x4 len 触发deq
+    txBuf[0+3] = 8'h04;
     txBuf[1+3] = 8'h00;
-    spi_trans( (16'h0202), (`SPI_WRITE), (2), (`IF_IDX(0)) );
+    spi_trans( (16'h0302), (`SPI_WRITE), (2), (`IF_IDX(0)) );
+    spi_trans( (16'h0306), (`SPI_WRITE), (2), (`IF_IDX(0)) );
 
     //无子报文
     txBuf[0+3] = 8'h00;
@@ -519,14 +521,13 @@ initial begin
     spi_trans( (16'h1000), (`SPI_WRITE), (4), (`IF_IDX(0)) ); //写入SM1
 
     //发布请求
-    txBuf[0+3] = 8'h04;
-    txBuf[1+3] = 8'h00;
-    spi_trans( (16'h21), (`SPI_WRITE), (2), (`IF_IDX(0)) );//写入长度
-
     txBuf[0+3] = 8'h01;
     spi_trans( (16'h20), (`SPI_WRITE), (1), (`IF_IDX(0)) );//发送SM0 接收SM0, 请求发送
     @(posedge isResp) #5 begin end
 
+    rxBuf[0+3] = 0;
+    spi_trans( (16'h803), (`SPI_READ), (1), (`IF_IDX(0)) );//读一下SM0的切换地址，将fifo弹出
+
   end
 
 
@@ -558,10 +559,11 @@ initial begin
 
 
     $fdisplay(spidata_file, "--->>>设置顺序地址");
-    //设置SM1在写入0xd地址触发enq
-    txBuf[0+3] = 8'h0d;
+    //设置SM1在写入0xe len触发enq
+    txBuf[0+3] = 8'h0e;
     txBuf[1+3] = 8'h00;
-    spi_trans( (16'h0202), (`SPI_WRITE), (2), (`IF_IDX(0)) );
+    spi_trans( (16'h0302), (`SPI_WRITE), (2), (`IF_IDX(0)) );
+    spi_trans( (16'h0306), (`SPI_WRITE), (2), (`IF_IDX(0)) );
 
     txBuf[0+3] = 8'h00;
     txBuf[1+3] = 8'ha0;//heeader length 10
@@ -584,15 +586,14 @@ initial begin
     spi_trans( (16'h1000), (`SPI_WRITE), (14), (`IF_IDX(0)) ); //写入SM1
 
 
-
     //发布请求
-    txBuf[0+3] = 8'h0e;
-    txBuf[1+3] = 8'h00;
-    spi_trans( (16'h21), (`SPI_WRITE), (2), (`IF_IDX(0)) );//写入长度
-
     txBuf[0+3] = 8'h01;
     spi_trans( (16'h20), (`SPI_WRITE), (1), (`IF_IDX(0)) );//发送SM0 接收SM0, 请求发送
     @(posedge isResp) #5 begin end
+
+    rxBuf[0+3] = 0;
+    spi_trans( (16'h80D), (`SPI_READ), (1), (`IF_IDX(0)) );//读一下SM0的切换地址，将fifo弹出
+
   end
 
 
@@ -620,10 +621,11 @@ initial begin
   $display("read&write @ %d", s_ShinTop_Mst.interface__io_cReg_timeStamp);
   begin
 
-    //设置SM1在写入516地址触发enq
-    txBuf[0+3] = 8'h03;
+    //设置SM1在写入516 len触发enq
+    txBuf[0+3] = 8'h04;
     txBuf[1+3] = 8'h02;
-    spi_trans( (16'h0202), (`SPI_WRITE), (2), (`IF_IDX(0)) );
+    spi_trans( (16'h0302), (`SPI_WRITE), (2), (`IF_IDX(0)) );
+    spi_trans( (16'h0306), (`SPI_WRITE), (2), (`IF_IDX(0)) );
 
 
     txBuf[0+3] = 8'h20;
@@ -703,15 +705,13 @@ initial begin
 
 
     //发布请求
-    txBuf[0+3] = 8'h04;
-    txBuf[1+3] = 8'h02;
-    spi_trans( (16'h21), (`SPI_WRITE), (2), (`IF_IDX(0)) );//写入长度
-
     txBuf[0+3] = 8'h01;
     spi_trans( (16'h20), (`SPI_WRITE), (1), (`IF_IDX(0)) );//发送SM0 接收SM0, 请求发送
     @(posedge isResp) #5 begin end
   end
 
+    spi_trans( (16'ha03), (`SPI_READ), (1), (`IF_IDX(0)) );//读一下SM0的切换地址，将fifo弹出
+
 
 
   // 同步
@@ -735,10 +735,11 @@ initial begin
 
 
 
-    //设置SM1在写入0x3地址触发enq
-    txBuf[0+3] = 8'h17;
+    //设置SM1在写入 0x18 len触发enq
+    txBuf[0+3] = 8'h18;
     txBuf[1+3] = 8'h00;
-    spi_trans( (16'h0202), (`SPI_WRITE), (2), (`IF_IDX(0)) );
+    spi_trans( (16'h0302), (`SPI_WRITE), (2), (`IF_IDX(0)) );
+    spi_trans( (16'h0306), (`SPI_WRITE), (2), (`IF_IDX(0)) );
 
     txBuf[0+3] = 8'h01;
     txBuf[1+3] = 8'h40;//heeader length 20
@@ -778,13 +779,12 @@ initial begin
     spi_trans( (16'h24), (`SPI_WRITE), (2), (`IF_IDX(0)) ); //写入替换时间戳替换地址寄存器
 
     //发布请求
-    txBuf[0+3] = 8'h18;
-    txBuf[1+3] = 8'h00;
-    spi_trans( (16'h21), (`SPI_WRITE), (2), (`IF_IDX(0)) );//写入长度
-
     txBuf[0+3] = 8'h01;
     spi_trans( (16'h20), (`SPI_WRITE), (1), (`IF_IDX(0)) );//发送SM0 接收SM0, 请求发送
-    @(posedge isResp) #5 begin end
+    @(posedge isResp) #5 begin
+      spi_trans( (16'h817), (`SPI_READ), (1), (`IF_IDX(0)) );//读一下SM0的切换地址，将fifo弹出
+    end
+
 
     //清除替换时间戳替换地址
     txBuf[0+3] = 8'h00;
@@ -795,10 +795,11 @@ initial begin
 
     //设定sync信号
 
-    //设置SM1在写入51地址触发enq
-    txBuf[0+3] = 8'd51;
+    //设置SM1在写入52 len触发enq
+    txBuf[0+3] = 8'd52;
     txBuf[1+3] = 8'h00;
-    spi_trans( (16'h0202), (`SPI_WRITE), (2), (`IF_IDX(0)) );
+    spi_trans( (16'h0302), (`SPI_WRITE), (2), (`IF_IDX(0)) );
+    spi_trans( (16'h0306), (`SPI_WRITE), (2), (`IF_IDX(0)) );
 
     //header
     txBuf[0+3] = 8'h03;
@@ -886,18 +887,15 @@ initial begin
     spi_trans( (16'h1000), (`SPI_WRITE), (52), (`IF_IDX(0)) ); //写入SM1
 
     //发布请求
-    txBuf[0+3] = 8'd52;
-    txBuf[1+3] = 8'h00;
-    spi_trans( (16'h21), (`SPI_WRITE), (2), (`IF_IDX(0)) );//写入长度
-
     txBuf[0+3] = 8'h01;
     spi_trans( (16'h20), (`SPI_WRITE), (1), (`IF_IDX(0)) );//发送SM0 接收SM0, 请求发送
     @(posedge isResp) #5 begin end
 
+    spi_trans( (16'h833), (`SPI_READ), (1), (`IF_IDX(0)) );//读一下SM0的切换地址，将fifo弹出
   end
 
+
   //清脉冲
-    //设置SM1在写入19地址触发enq
     txBuf[0+3] = 0;  //负载0x122 sync0脉冲宽度
     txBuf[1+3] = 0;  //负载0x123
     txBuf[2+3] = 0;  //负载0x124 sync1脉冲宽度