ruige/eb001
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

移动smEnq/Deq addr寄存器，合并为len，删除txlength寄存器

Browse Source
This commit is contained in:
Ruige Lee
2025-05-20 11:32:03 +08:00
parent 090a10ff17
commit cb30c29e07
5 changed files with 110 additions and 126 deletions
Download Patch File Download Diff File Expand all files Collapse all files

61
src/main/scala/backBoard/shin/Interface.scala
View File

@@ -39,9 +39,9 @@ class CommonRegisterBundle extends Bundle{
val syncPeroid = UInt(32.W)
val smEnqAddr = Vec(8, UInt(11.W)) //触发SM切换缓冲区的地址 （或读或写）
val smDeqAddr = Vec(8, UInt(11.W)) //触发SM切换缓冲区的地址 （或读或写）
// val smEnqAddr = Vec(8, UInt(11.W)) //触发SM切换缓冲区的地址 （或读或写）
// val smDeqAddr = Vec(8, UInt(11.W)) //触发SM切换缓冲区的地址 （或读或写）
val smTrigLen = Vec(8, UInt(11.W)) //触发SM切换缓冲区的地址 （或读或写）
}
@@ -51,7 +51,7 @@ class MasterRegisterBundle extends Bundle{
val txSM = UInt(2.W)
val rxSM = UInt(2.W)
val txLength = UInt(12.W)
// val txLength = UInt(12.W)
// val txStatus = UInt(16.W)
val rplTimeStampTx = UInt(16.W)
@@ -156,7 +156,7 @@ class InterfaceIO extends Bundle{
val txReq = Valid(new Bundle{
val txSM = UInt(2.W)
val rxSM = UInt(2.W)
val txLength = UInt(12.W)
// val txLength = UInt(12.W)
}) //发送请求和SM代号
@@ -182,9 +182,6 @@ class InterfaceIO extends Bundle{
// val smEnqAddr = Output(Vec(8, UInt(16.W))) //触发SM切换缓冲区的地址 （或读或写）
// val smDeqAddr = Output(Vec(8, UInt(16.W))) //触发SM切换缓冲区的地址 （或读或写）
// val mstTimeStamp = Input(UInt(64.W)) //主站时间戳
val slvDeltaTime = Input(UInt(32.W)) //从站时间戳差值
val mstDeltaTime = Input(UInt(32.W))
val deltaFinal = Input(UInt(32.W))
@@ -249,7 +246,7 @@ abstract class InterfaceBase extends Module{
(addr === "h20".U & isMstMode) -> Cat(mReg.rxSM, mReg.txSM, 0.U(1.W) ),
(addr === "h21".U & isMstMode) -> mReg.txLength,
//(addr === "h21".U & isMstMode) -> mReg.txLength,
(addr === "h24".U & isMstMode) -> mReg.rplTimeStampTx(7,0),
(addr === "h25".U & isMstMode) -> mReg.rplTimeStampTx(15,8),
@@ -357,9 +354,18 @@ abstract class InterfaceBase extends Module{
(addr === "h145".U & isSlvMode) -> sReg.syncOffset(3)(15,8),
(addr === "h146".U & isSlvMode) -> sReg.syncOffset(3)(23,16),
(addr === "h147".U & isSlvMode) -> sReg.syncOffset(3)(31,24),
)
) ++
( 0 until 8 ).map{ i =>
( addr === ("h302".U + (i*4).U) ) -> cReg.smTrigLen(i)(7,0)
} ++
( 0 until 8 ).map{ i =>
( addr === ("h303".U + (i*4).U) ) -> cReg.smTrigLen(i)(10,8)
} ++
Seq()
)
}
@@ -455,7 +461,7 @@ trait InterfaceMCUop{ this: InterfaceBase =>
mReg.txSM := RegEnable( dataw(2,1), 0.U, isEnW & addrSel === "h20".U )
mReg.rxSM := RegEnable( dataw(4,3), 0.U, isEnW & addrSel === "h20".U )
mReg.txLength := Cat( RegEnable( dataw, 0.U, isEnW & addrSel === "h22".U ), RegEnable( dataw, 0.U, isEnW & addrSel === "h21".U ) )
// mReg.txLength := Cat( RegEnable( dataw, 0.U, isEnW & addrSel === "h22".U ), RegEnable( dataw, 0.U, isEnW & addrSel === "h21".U ) )
mReg.rplTimeStampTx :=
Cat(
@@ -529,16 +535,12 @@ trait InterfaceCheckSM{ this: InterfaceBase =>
val isEnR: Bool
for( i <- 0 until 8 ){
cReg.smEnqAddr(i) :=
cReg.smTrigLen(i) :=
Cat(
RegEnable( dataw, 0.U, isEnW & addrSel === ("h201".U + (i*2).U) ),
RegEnable( dataw, 0.U, isEnW & addrSel === ("h200".U + (i*2).U) ),
)
cReg.smDeqAddr(i) :=
Cat(
RegEnable( dataw, 0.U, isEnW & addrSel === ("h301".U + (i*2).U) ),
RegEnable( dataw, 0.U, isEnW & addrSel === ("h300".U + (i*2).U) ),
RegEnable( dataw, 0.U, isEnW & addrSel === ("h303".U + (i*4).U) ),
RegEnable( dataw, 0.U, isEnW & addrSel === ("h302".U + (i*4).U) ),
)
}
@@ -567,15 +569,15 @@ trait InterfaceCheckSM{ this: InterfaceBase =>
io.sram_w(2).enw := isEnW & (( addrSel & "hF800".U ) === "h3000".U)
io.sram_w(3).enw := isEnW & (( addrSel & "hF800".U ) === "h4000".U)
io.dSMdeq(0) := isEnR & (( addrSel & "hF800".U ) === "h0800".U) & (addrSel(10,0) === cReg.smDeqAddr(0))
io.dSMdeq(1) := isEnR & (( addrSel & "hF800".U ) === "h0800".U) & (addrSel(10,0) === cReg.smDeqAddr(2))
io.dSMdeq(2) := isEnR & (( addrSel & "hF800".U ) === "h0800".U) & (addrSel(10,0) === cReg.smDeqAddr(4))
io.dSMdeq(3) := isEnR & (( addrSel & "hF800".U ) === "h0800".U) & (addrSel(10,0) === cReg.smDeqAddr(6))
io.dSMdeq(0) := isEnR & (( addrSel & "hF800".U ) === "h0800".U) & (addrSel(10,0) === cReg.smTrigLen(0) - 1.U)
io.dSMdeq(1) := isEnR & (( addrSel & "hF800".U ) === "h0800".U) & (addrSel(10,0) === cReg.smTrigLen(2) - 1.U)
io.dSMdeq(2) := isEnR & (( addrSel & "hF800".U ) === "h0800".U) & (addrSel(10,0) === cReg.smTrigLen(4) - 1.U)
io.dSMdeq(3) := isEnR & (( addrSel & "hF800".U ) === "h0800".U) & (addrSel(10,0) === cReg.smTrigLen(6) - 1.U)
io.uSMenq(0) := isEnW & (( addrSel & "hF800".U ) === "h1000".U) & (addrSel(10,0) === cReg.smEnqAddr(1))
io.uSMenq(1) := isEnW & (( addrSel & "hF800".U ) === "h2000".U) & (addrSel(10,0) === cReg.smEnqAddr(3))
io.uSMenq(2) := isEnW & (( addrSel & "hF800".U ) === "h3000".U) & (addrSel(10,0) === cReg.smEnqAddr(5))
io.uSMenq(3) := isEnW & (( addrSel & "hF800".U ) === "h4000".U) & (addrSel(10,0) === cReg.smEnqAddr(7))
io.uSMenq(0) := isEnW & (( addrSel & "hF800".U ) === "h1000".U) & (addrSel(10,0) === cReg.smTrigLen(1) - 1.U)
io.uSMenq(1) := isEnW & (( addrSel & "hF800".U ) === "h2000".U) & (addrSel(10,0) === cReg.smTrigLen(3) - 1.U)
io.uSMenq(2) := isEnW & (( addrSel & "hF800".U ) === "h3000".U) & (addrSel(10,0) === cReg.smTrigLen(5) - 1.U)
io.uSMenq(3) := isEnW & (( addrSel & "hF800".U ) === "h4000".U) & (addrSel(10,0) === cReg.smTrigLen(7) - 1.U)
}
trait InterfaceLVDSop{ this: InterfaceBase =>
@@ -723,11 +725,10 @@ with InterfaceSync
io.txReq.bits.txSM := mReg.txSM
io.txReq.bits.rxSM := mReg.rxSM
io.txReq.bits.txLength := mReg.txLength
// io.txReq.bits.txLength := //mReg.txLength
io.txReq.valid := isEnW & addrSel === "h20".U & dataw.extract(0) === "b1".U //& mReg.txLength =/= 0.U
// io.smEnqAddr := cReg.smEnqAddr
// io.smDeqAddr := cReg.smDeqAddr
sReg.localDevIndex := io.localDevIndex