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反转FSMC信号电平，尝试测试

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This commit is contained in:
RuigeLee
2024-03-06 17:41:28 +08:00
parent ea226e913a
commit ca60205abc
2 changed files with 30 additions and 30 deletions
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24
src/main/scala/backBoard/BackBoardMst.scala
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@@ -11,10 +11,10 @@ class FSMC_Port_Bundle extends Bundle{
val ADIn = Input(UInt(16.W)) val ADIn = Input(UInt(16.W))
val ADOut = Output(UInt(16.W)) val ADOut = Output(UInt(16.W))
val ADOEn = Output(Bool()) val ADOEn = Output(Bool())
val cs = Input(Bool()) val csn = Input(Bool())
val rd = Input(Bool()) val rdn = Input(Bool())
val wr = Input(Bool()) val wrn = Input(Bool())
val adv = Input(Bool()) val advn = Input(Bool())
} }
@@ -120,10 +120,10 @@ trait BackBoardMstFSMC{ this: BackBoardMstBase =>
withClockAndReset( io.ides_pclk.asClock, reset ){//100M withClockAndReset( io.ides_pclk.asClock, reset ){//100M
val fsmcCSSync = ShiftRegisters( io.FSMC.cs, 3, false.B, true.B ) val fsmcCSSync = ShiftRegisters( ~io.FSMC.csn, 3, false.B, true.B )
val fsmcRDSync = ShiftRegisters( io.FSMC.rd, 3, false.B, true.B ) val fsmcRDSync = ShiftRegisters( ~io.FSMC.rdn, 3, false.B, true.B )
val fsmcWRSync = ShiftRegisters( io.FSMC.wr, 3, false.B, true.B ) val fsmcWRSync = ShiftRegisters( ~io.FSMC.wrn, 3, false.B, true.B )
val fsmcADVSync = ShiftRegisters( io.FSMC.adv, 3, false.B, true.B ) val fsmcADVSync = ShiftRegisters( ~io.FSMC.advn, 3, false.B, true.B )
io.FSMC.ADOEn := fsmcRDSync(1) io.FSMC.ADOEn := fsmcRDSync(1)
@@ -135,8 +135,8 @@ trait BackBoardMstFSMC{ this: BackBoardMstBase =>
val regOut = Wire(UInt(16.W)) val regOut = Wire(UInt(16.W))
val fsmcCSWRSync = ShiftRegisters( io.FSMC.cs & io.FSMC.wr, 3, false.B, true.B ) val fsmcCSWRSync = ShiftRegisters( ~io.FSMC.csn & ~io.FSMC.wrn, 3, false.B, true.B )
val fsmcCSRDSync = ShiftRegisters( io.FSMC.cs & io.FSMC.rd, 3, false.B, true.B ) val fsmcCSRDSync = ShiftRegisters( ~io.FSMC.csn & ~io.FSMC.rdn, 3, false.B, true.B )
@@ -257,8 +257,8 @@ trait BackBoardMstSim{ this: BackBoardMstLVDSBase =>
abstract class BackBoardMstLVDSBase extends BackBoardMstBase abstract class BackBoardMstLVDSBase extends BackBoardMstBase
// with BackBoardMstFSMC with BackBoardMstFSMC
with BackBoardMstSim // with BackBoardMstSim
{ {

36
src/main/verilog/backBoardMstTop.v
View File

@@ -15,10 +15,10 @@ module master_top(
inout [15:0] io_FSMC_AD, inout [15:0] io_FSMC_AD,
input io_FSMC_cs, input io_FSMC_csn,
input io_FSMC_rd, input io_FSMC_rdn,
input io_FSMC_wr, input io_FSMC_wrn,
input io_FSMC_adv input io_FSMC_advn
); );
wire [15:0] io_FSMC_ADIn; wire [15:0] io_FSMC_ADIn;
@@ -125,21 +125,21 @@ CLKDIV Inst5_CLKDIVC(
BackBoardMst i_BackBoardMst( BackBoardMst i_BackBoardMst(
// .io_FSMC_ADIn (io_FSMC_ADIn), .io_FSMC_ADIn (io_FSMC_ADIn),
// .io_FSMC_ADOut(io_FSMC_ADOut), .io_FSMC_ADOut(io_FSMC_ADOut),
// .io_FSMC_ADOEn(io_FSMC_ADOEn), .io_FSMC_ADOEn(io_FSMC_ADOEn),
// .io_FSMC_cs(io_FSMC_cs), .io_FSMC_csn(io_FSMC_csn),
// .io_FSMC_rd(io_FSMC_rd), .io_FSMC_rdn(io_FSMC_rdn),
// .io_FSMC_wr(io_FSMC_wr), .io_FSMC_wrn(io_FSMC_wrn),
// .io_FSMC_adv(io_FSMC_adv), .io_FSMC_advn(io_FSMC_advn),
.io_FSMC_ADIn ('d0), // .io_FSMC_ADIn ('d0),
.io_FSMC_ADOut(), // .io_FSMC_ADOut(),
.io_FSMC_ADOEn(), // .io_FSMC_ADOEn(),
.io_FSMC_cs(1'b0), // .io_FSMC_csn(1'b1),
.io_FSMC_rd(1'b0), // .io_FSMC_rdn(1'b1),
.io_FSMC_wr(1'b0), // .io_FSMC_wrn(1'b1),
.io_FSMC_adv(1'b0), // .io_FSMC_advn(1'b1),
.reset(~rst_n), .reset(~rst_n),
.clock(clk_10m_a), .clock(clk_10m_a),