From ca60205abc2fdcc47807dc970448036894ee23fc Mon Sep 17 00:00:00 2001 From: RuigeLee Date: Wed, 6 Mar 2024 17:41:28 +0800 Subject: [PATCH] =?UTF-8?q?=E5=8F=8D=E8=BD=ACFSMC=E4=BF=A1=E5=8F=B7?= =?UTF-8?q?=E7=94=B5=E5=B9=B3=EF=BC=8C=E5=B0=9D=E8=AF=95=E6=B5=8B=E8=AF=95?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- src/main/scala/backBoard/BackBoardMst.scala | 24 +++++++------- src/main/verilog/backBoardMstTop.v | 36 ++++++++++----------- 2 files changed, 30 insertions(+), 30 deletions(-) diff --git a/src/main/scala/backBoard/BackBoardMst.scala b/src/main/scala/backBoard/BackBoardMst.scala index 43ce44f..0d50ec1 100644 --- a/src/main/scala/backBoard/BackBoardMst.scala +++ b/src/main/scala/backBoard/BackBoardMst.scala @@ -11,10 +11,10 @@ class FSMC_Port_Bundle extends Bundle{ val ADIn = Input(UInt(16.W)) val ADOut = Output(UInt(16.W)) val ADOEn = Output(Bool()) - val cs = Input(Bool()) - val rd = Input(Bool()) - val wr = Input(Bool()) - val adv = Input(Bool()) + val csn = Input(Bool()) + val rdn = Input(Bool()) + val wrn = Input(Bool()) + val advn = Input(Bool()) } @@ -120,10 +120,10 @@ trait BackBoardMstFSMC{ this: BackBoardMstBase => withClockAndReset( io.ides_pclk.asClock, reset ){//100M - val fsmcCSSync = ShiftRegisters( io.FSMC.cs, 3, false.B, true.B ) - val fsmcRDSync = ShiftRegisters( io.FSMC.rd, 3, false.B, true.B ) - val fsmcWRSync = ShiftRegisters( io.FSMC.wr, 3, false.B, true.B ) - val fsmcADVSync = ShiftRegisters( io.FSMC.adv, 3, false.B, true.B ) + val fsmcCSSync = ShiftRegisters( ~io.FSMC.csn, 3, false.B, true.B ) + val fsmcRDSync = ShiftRegisters( ~io.FSMC.rdn, 3, false.B, true.B ) + val fsmcWRSync = ShiftRegisters( ~io.FSMC.wrn, 3, false.B, true.B ) + val fsmcADVSync = ShiftRegisters( ~io.FSMC.advn, 3, false.B, true.B ) io.FSMC.ADOEn := fsmcRDSync(1) @@ -135,8 +135,8 @@ trait BackBoardMstFSMC{ this: BackBoardMstBase => val regOut = Wire(UInt(16.W)) - val fsmcCSWRSync = ShiftRegisters( io.FSMC.cs & io.FSMC.wr, 3, false.B, true.B ) - val fsmcCSRDSync = ShiftRegisters( io.FSMC.cs & io.FSMC.rd, 3, false.B, true.B ) + val fsmcCSWRSync = ShiftRegisters( ~io.FSMC.csn & ~io.FSMC.wrn, 3, false.B, true.B ) + val fsmcCSRDSync = ShiftRegisters( ~io.FSMC.csn & ~io.FSMC.rdn, 3, false.B, true.B ) @@ -257,8 +257,8 @@ trait BackBoardMstSim{ this: BackBoardMstLVDSBase => abstract class BackBoardMstLVDSBase extends BackBoardMstBase -// with BackBoardMstFSMC -with BackBoardMstSim +with BackBoardMstFSMC +// with BackBoardMstSim { diff --git a/src/main/verilog/backBoardMstTop.v b/src/main/verilog/backBoardMstTop.v index ca3aaf4..a8250ee 100644 --- a/src/main/verilog/backBoardMstTop.v +++ b/src/main/verilog/backBoardMstTop.v @@ -15,10 +15,10 @@ module master_top( inout [15:0] io_FSMC_AD, - input io_FSMC_cs, - input io_FSMC_rd, - input io_FSMC_wr, - input io_FSMC_adv + input io_FSMC_csn, + input io_FSMC_rdn, + input io_FSMC_wrn, + input io_FSMC_advn ); wire [15:0] io_FSMC_ADIn; @@ -125,21 +125,21 @@ CLKDIV Inst5_CLKDIVC( BackBoardMst i_BackBoardMst( - // .io_FSMC_ADIn (io_FSMC_ADIn), - // .io_FSMC_ADOut(io_FSMC_ADOut), - // .io_FSMC_ADOEn(io_FSMC_ADOEn), - // .io_FSMC_cs(io_FSMC_cs), - // .io_FSMC_rd(io_FSMC_rd), - // .io_FSMC_wr(io_FSMC_wr), - // .io_FSMC_adv(io_FSMC_adv), + .io_FSMC_ADIn (io_FSMC_ADIn), + .io_FSMC_ADOut(io_FSMC_ADOut), + .io_FSMC_ADOEn(io_FSMC_ADOEn), + .io_FSMC_csn(io_FSMC_csn), + .io_FSMC_rdn(io_FSMC_rdn), + .io_FSMC_wrn(io_FSMC_wrn), + .io_FSMC_advn(io_FSMC_advn), - .io_FSMC_ADIn ('d0), - .io_FSMC_ADOut(), - .io_FSMC_ADOEn(), - .io_FSMC_cs(1'b0), - .io_FSMC_rd(1'b0), - .io_FSMC_wr(1'b0), - .io_FSMC_adv(1'b0), + // .io_FSMC_ADIn ('d0), + // .io_FSMC_ADOut(), + // .io_FSMC_ADOEn(), + // .io_FSMC_csn(1'b1), + // .io_FSMC_rdn(1'b1), + // .io_FSMC_wrn(1'b1), + // .io_FSMC_advn(1'b1), .reset(~rst_n), .clock(clk_10m_a),